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Stratix GX FPGA Family
December 2004, ver. 2.2
Data Sheet
Introduction
The Stratix(R) GX family of devices is Altera's second FPGA family to combine high-speed serial transceivers with a scalable, high-performance logic array. Stratix GX devices include 4 to 20 high-speed transceiver channels, each incorporating clock data recovery (CDR) technology and embedded SERDES capability at data rates of up to 3.1875 gigabits per second (Gbps). These transceivers are grouped by four-channel transceiver blocks, and are designed for low power consumption and small die size. The Stratix GX FPGA technology is built upon the Stratix architecture, and offers a 1.5-V logic array with unmatched performance, flexibility, and time-to-market capabilities. This scalable, high-performance architecture makes Stratix GX devices ideal for high-speed backplane interface, chip-to-chip, and communications protocol-bridging applications.
Features
Transceiver block features are as follows: High-speed serial transceiver channels with CDR provides 500-megabits per second (Mbps) to 3.1875-Gbps full-duplex operation Devices are available with 4, 8, 16, or 20 high-speed serial transceiver channels providing up to 127.5 Gbps of full-duplex serial bandwidth Support for transceiver-based protocols, including 10 Gigabit Ethernet attachment unit interface (XAUI), Gigabit Ethernet (GigE), and SONET/SDH Compatible with PCI Express, SMPTE 292M, Fibre Channel, and Serial RapidIO I/O standards Programmable differential output voltage (VOD), pre-emphasis, and equalization settings for improved signal integrity Individual transmitter and receiver channel power-down capability implemented automatically by the Quartus(R) II software for reduced power consumption during non-operation Programmable transceiver-to-FPGA interface with support for 8-, 10-, 16-, and 20-bit wide data paths 1.5-V pseudo current mode logic (PCML) for 500 Mbps to 3.1875 Gbps Support for LVDS, LVPECL, and 3.3-V PCML on reference clocks and receiver input pins (AC-coupled) Built-in self test (BIST) Hot insertion/removal protection circuitry
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Stratix GX FPGA Family

Pattern detector and word aligner supports programmable patterns 8B/10B encoder/decoder performs 8- to 10-bit encoding and 10to 8-bit decoding Rate matcher compliant with IEEE 802.3-2002 for GigE mode and with IEEE 802-3ae for XAUI mode Channel bonding compliant with IEEE 802.3ae (for XAUI mode only) Device can bypass some transceiver block features if necessary
FPGA features are as follows: 10,570 to 41,250 logic elements (LEs); see Table 1 Up to 3,423,744 RAM bits (427,968 bytes) available without reducing logic resources TriMatrixTM memory consisting of three RAM block sizes to implement true dual-port memory and first-in-out (FIFO) buffers Up to 16 global clock networks with up to 22 regional clock networks per device region High-speed DSP blocks provide dedicated implementation of multipliers (faster than 300 MHz), multiply-accumulate functions, and finite impulse response (FIR) filters Up to eight general usage phase-locked loops (four enhanced PLLs and four fast PLLs) per device provide spread spectrum, programmable bandwidth, clock switchover, real-time PLL reconfiguration, and advanced multiplication and phase shifting Support for numerous single-ended and differential I/O standards High-speed source-synchronous differential I/O support on up to 45 channels for 1-Gbps performance Support for source-synchronous bus standards, including 10-Gigabit Ethernet XSBI, Parallel RapidIO, UTOPIA IV, Network Packet Streaming Interface (NPSI), HyperTransportTM technology, SPI-4 Phase 2 (POS-PHY Level 4), and SFI-4 Support for high-speed external memory, including zero bus turnaround (ZBT) SRAM, quad data rate (QDR and QDRII) SRAM, double data rate (DDR) SDRAM, DDR fast cycle RAM (FCRAM), and single data rate (SDR) SDRAM Support for multiple intellectual property megafunctions from Altera(R) MegaCore(R) functions and Altera Megafunction Partners Program (AMPPSM) megafunctions Support for remote configuration updates Dynamic phase alignment on LVDS receiver channels
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Features
Table 1. Stratix GX Device Features Feature
LEs Transceiver channels Source-synchronous channels M512 RAM blocks (32 x 18 bits) M4K RAM blocks (128 x 36 bits) M-RAM blocks (4K x144 bits) Total RAM bits Digital signal processing (DSP) blocks Embedded multipliers (1) PLLs Note to Table 1:
(1) This parameter lists the total number of 9- x 9-bit multipliers for each device. For the total number of 18- x 18-bit multipliers per device, divide the total number of 9- x 9-bit multipliers by 2. For the total number of 36- x 36-bit multipliers per device, decide the total number of 9- x 9-bit multipliers by 8.
EP1SGX10C EP1SGX10D
10,570 4, 8 22 94 60 1 920,448 6 48 4
EP1SGX25C EP1SGX25D EP1SGX25F
25,660 4, 8, 16 39 224 138 2 1,944,576 10 80 4
EP1SGX40D EP1SGX40G
41,250 8, 20 45 384 183 4 3,423,744 14 112 8
Stratix GX devices are available in space-saving FineLine BGA(R) packages (refer to Tables 2 and 3), and in multiple speed grades (refer to Table 4). Stratix GX devices support vertical migration within the same package (that is, the designer can migrate between the EP1SGX10C and EP1SGX25C devices in the 672-pin FineLine BGA package). See the Stratix GX device pin tables for more information. Vertical migration means that designers can migrate to devices whose dedicated pins, configuration pins, and power pins are the same for a given package across device densities. For I/O pin migration across densities, the designer must cross-reference the available I/O pins using the device pinouts for all planned densities of a given package type, to identify which I/O pins it is possible to migrate. The Quartus II software can automatically cross reference and place all pins for migration when given a device migration list.
Table 2. Stratix GX Package Options & I/O Pin Counts (Part 1 of 2) Note (1) Device
EP1SGX10C EP1SGX10D EP1SGX25C
672-Pin FineLine BGA
362 362 455
1,020-Pin FineLine BGA
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Table 2. Stratix GX Package Options & I/O Pin Counts (Part 2 of 2) Note (1) Device
EP1SGX25D EP1SGX25F EP1SGX40D EP1SGX40G Note to Table 2:
(1) The number of I/O pins listed for each package includes dedicated clock pins and dedicated fast I/O pins. However, these numbers do not include high-speed or clock reference pins for high-speed I/O standards.
672-Pin FineLine BGA
455
1,020-Pin FineLine BGA
607 607 624 624
Table 3. Stratix GX FineLine BGA Package Sizes Dimension
Pitch (mm) Area (mm2)
672 Pin
1.00 729 27 x 27
1,020 Pin
1.00 1,089 33 x 33
Length x width (mm x mm)
Table 4. Stratix GX Device Speed Grades Device
EP1SGX10 EP1SGX25 EP1SGX40
672-Pin FineLine BGA
-5, -6, -7 -5, -6, -7
1,020-pin FineLine BGA
-5, -6, -7 -5, -6, -7
High-Speed I/O Interface Functional Description
The Stratix GX device family supports high-speed serial transceiver blocks with CDR circuitry as well as source-synchronous interfaces. The channels on the right side of the device use an embedded circuit dedicated for receiving and transmitting high-speed serial data streams to and from the system board. These channels are clustered in a four-channel serial transceiver building block and deliver high-speed bidirectional point-to-point data transmissions to provide up to 3.1875 Gbps of full-duplex data transmission per channel. The channels on the left side of the device support source-synchronous data transfers at up to 1 Gbps using LVDS, LVPECL, 3.3-V PCML, or HyperTransport technology I/O standards. Figure 1 shows the Stratix GX I/O blocks. The differential source-synchronous serial interface is described in "Principles of SERDES Operation" on page 47 and the high-speed serial interface is described in "Transceiver Blocks" on page 8.
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FPGA Functional Description
Figure 1. Stratix GX I/O Blocks
DQST9
PLL7
Note (1)
DQST5 9 PLL5 10 DQST4 PLL11 DQST3 DQST2
Bank 4
DQST8
DQST7
Bank 3
DQST6
DQST1
DQST0
VREF1B3 VREF2B3 VREF3B3 VREF4B3 VREF5B3
VREF1B4 VREF2B4 VREF3B4 VREF4B4 VREF5B4
VREF1B2 VREF2B2 VREF3B2 VREF4B2
I/O Bank 13 (5) LVDS, LVPECL, 3.3-V PCML, and HyperTransport I/O Block and Regular I/O Pins (3)
Bank 2
(4)
I/O Banks 3, 4, 9 & 10 Support All Single-Ended I/O Standards (2)
I/O Bank 14 (5)
PLL1
PLL2 VREF1B1 VREF2B1 VREF3B1 VREF4B1
I/O Banks 1 and 2 Support All Single-Ended I/O Standards Except Differential HSTL Output Clocks, Differential SSTL-2 Output Clocks, HSTL Class II, GTL, SSTL-18 Class II, PCI, PCI-X, and AGP 1x/2x
1.5-V PCML (5)
I/O Bank 17 (5)
Bank 1
(4) LVDS, LVPECL, 3.3-V PCML, and HyperTransport I/O Block and Regular I/O Pins (3)
I/O Banks 7, 8, 11 & 12 Support All Single-Ended I/O Standards (2)
I/O Bank 16 (5)
I/O Bank 15 (5)
Bank 8 11 DQSB6 DQSB5 12 PLL12 DQSB4 DQSB3 Bank 7
VREF5B7 VREF4B7 VREF3B7 VREF2B7 VREF1B7 VREF5B8 VREF4B8 VREF3B8 VREF2B8 VREF1B8
PLL8
DQSB9
DQSB8
DQSB7
PLL6
DQSB2
DQSB1
DQSB0
Notes to Figure 1:
(1) (2) (3) (4) (5) Figure 1 is a top view of the Stratix GX silicon die. Banks 9 through 12 are enhanced PLL external clock output banks. If the high-speed differential I/O pins are not used for high-speed differential signaling, they can support all of the I/O standards except HSTL class I and II, GTL, SSTL-18 Class II, PCI, PCI-X, and AGP 1x/2x. For guidelines for placing single-ended I/O pads next to differential I/O pads, see the Selectable I/O Standards in Stratix & Stratix GX Devices chapter in the Stratix Device Handbook, Volume 2. These I/O banks in Stratix GX devices also support the LVDS, LVPECL, and 3.3-V PCML I/O standards on reference clocks and receiver input pins (AC coupled).
FPGA Functional Description
Stratix GX devices contain a two-dimensional row- and column-based architecture to implement custom logic. A series of column and row interconnects of varying length and speed provide signal interconnects between logic array blocks (LABs), memory block structures, and DSP blocks.
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The logic array consists of LABs, with 10 logic elements (LEs) in each LAB. An LE is a small unit of logic providing efficient implementation of user logic functions. LABs are grouped into rows and columns across the device. M512 RAM blocks are simple dual-port memory blocks with 512 bits plus parity (576 bits). These blocks provide dedicated simple dual-port or single-port memory up to 18-bits wide at up to 318 MHz. M512 blocks are grouped into columns across the device in between certain LABs. M4K RAM blocks are true dual-port memory blocks with 4K bits plus parity (4,608 bits). These blocks provide dedicated true dual-port, simple dual-port, or single-port memory up to 36-bits wide at up to 291 MHz. These blocks are grouped into columns across the device in between certain LABs. M-RAM blocks are true dual-port memory blocks with 512K bits plus parity (589,824 bits). These blocks provide dedicated true dual-port, simple dual-port, or single-port memory up to 144-bits wide at up to 269 MHz. Several M-RAM blocks are located individually or in pairs within the device's logic array. Digital signal processing (DSP) blocks can implement up to either eight full-precision 9 x 9-bit multipliers, four full-precision 18 x 18-bit multipliers, or one full-precision 36 x 36-bit multiplier with add or subtract features. These blocks also contain 18-bit input shift registers for digital signal processing applications, including FIR and infinite impulse response (IIR) filters. DSP blocks are grouped into two columns in each device. Each Stratix GX device I/O pin is fed by an I/O element (IOE) located at the end of LAB rows and columns around the periphery of the device. I/O pins support numerous single-ended and differential I/O standards. Each IOE contains a bidirectional I/O buffer and six registers for registering input, output, and output-enable signals. When used with dedicated clocks, these registers provide exceptional performance and interface support with external memory devices such as DDR SDRAM, FCRAM, ZBT, and QDR SRAM devices. High-speed serial interface channels support transfers at up to 840 Mbps using LVDS, LVPECL, 3.3-V PCML, or HyperTransport technology I/O standards. Figure 2 shows an overview of the Stratix GX device.
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FPGA Functional Description
Figure 2. Stratix GX Block Diagram
M512 RAM Blocks for Dual-Port Memory, Shift Registers, & FIFO Buffers DSP Blocks for Multiplication and Full Implementation of FIR Filters M4K RAM Blocks for True Dual-Port Memory & Other Embedded Memory Functions IOEs Support DDR, PCI, GTL+, SSTL-3, SSTL-2, HSTL, LVDS, LVPECL, PCML, HyperTransport & other I/O Standards
IOEs IOEs IOEs IOEs IOEs IOEs IOEs IOEs IOEs IOEs IOEs IOEs IOEs IOEs IOEs IOEs IOEs IOEs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs
IOEs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs
IOEs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs
IOEs LABs LABs LABs LABs
M-RAM Block
LABs
DSP Block
The number of M512 RAM, M4K RAM, and DSP blocks varies by device along with row and column numbers and M-RAM blocks. Table 5 lists the resources available in Stratix GX devices.
Table 5. Stratix GX Device Resources Device
EP1SGX10 EP1SGX25 EP1SGX40
M512 RAM M4K RAM Columns/Blocks Columns/Blocks
4 / 94 6 / 224 8 / 384 2 / 60 3 / 138 3 / 183
M-RAM Blocks
1 2 4
DSP Block Columns/Blocks
2/6 2 / 10 2 / 14
LAB Columns
40 62 77
LAB Rows
30 46 61
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Transceiver Blocks
Stratix GX devices incorporate dedicated embedded circuitry on the right side of the device, which contains up to 20 high-speed 3.1875-Gbps serial transceiver channels. Each Stratix GX transceiver block contains four fullduplex channels and supporting logic to transmit and receive high-speed serial data streams. The transceiver block uses the channels to deliver bidirectional point-to-point data transmissions with up to 3.1875 Gbps of data transition per channel. There are up to 20 transceiver channels available on a single Stratix GX device. Table 6 shows the number of transceiver channels available on each Stratix GX device.
Table 6. Stratix GX Transceiver Channels Device
EP1SGX10C EP1SGX10D EP1SGX25C EP1SGX25D EP1SGX25F EP1SGX40D EP1SGX40G
Number of Transceiver Channels
4 8 4 8 16 8 20
Figure 3 shows the elements of the transceiver block, including the four channels, supporting logic, and I/O buffers. Each transceiver channel consists of a receiver and transmitter. The supporting logic contains a transmitter PLL to generate a high-speed clock used by the four transmitters. The receiver PLL within each transceiver channel generates the receiver reference clocks. The supporting logic also contains state machines to manage rate matching for XAUI and GigE applications, in addition to channel bonding for XAUI applications.
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Transceiver Blocks
Figure 3. Stratix GX Transceiver Block
Receiver Channel 0 PLD Logic Array Channel 0 Transmitter Channel 0
Receiver Pins
Transmitter Pins
Receiver Channel 1 PLD Logic Array Channel 1 Transmitter Channel 1
Receiver Pins
Transmitter Pins
PLD Logic Array
XAUI Receiver State Machine
XAUI Transmitter State Machine
Channel Aligner State Machine
Transmitter PLL
PLD Logic Array
Receiver Channel 2 PLD Logic Array Channel 2 Transmitter Channel 2
Receiver Pins
Transmitter Pins
Receiver Channel 3 PLD Logic Array Channel 3 Transmitter Channel 3
Receiver Pins
Transmitter Pins
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Each Stratix GX transceiver channel consists of a transmitter and receiver. The transmitter contains the following:

Transmitter PLL Transmitter phase compensation FIFO buffer Byte serializer 8B/10B encoder Serializer (parallel to serial converter) Transmitter output buffer
The receiver contains the following:

Input buffer Clock recovery unit (CRU) Deserializer Pattern detector and word aligner Rate matcher and channel aligner 8B/10B decoder Receiver logic array interface
Designers can set all the Stratix GX transceiver functions through the Quartus II software. Designers can set programmable pre-emphasis, programmable equalizer, and programmable VOD dynamically as well. Each Stratix GX transceiver channel is also capable of BIST generation and verification in addition to various loopback modes. Figure 4 shows the block diagram for the Stratix GX transceiver channel. Stratix GX transceivers provide physical coding sublayer (PCS) and physical media attachment (PMA) implementation for protocols such as 10-gigabit XAUI and GigE. The PCS portion of the transceiver consists of the logic array interface, 8B/10B encoder/decoder, pattern detector, word aligner, rate matcher, channel aligner, and the BIST and pseudo-random binary sequence pattern generator/verifier. The PMA portion of the transceiver consists of the serializer/deserializer, the CRU, and the I/O buffers.
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(1)
Note to Figure 4:
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Channel 0 Receiver Deserializer Word Aligner Clock Recovery Unit Channel Aligner Rate Matcher 8B/10B Decoder Byte Deserializer Phase Compensation FIFO Reference Clock Receiver PLL
Figure 4. Stratix GX Transceiver Channel
To Channels 1-3 Transmitter
Note (1)
There are four transciever channels in a transceiver block.
Deserializer Byte Serializer Phase Compensation FIFO 8B/10B Encoder Transmitter PLL
Transceiver Blocks
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Transmitter Path
This section describes the data path through the Stratix GX transmitter (see Figure 4). Data travels through the Stratix GX transmitter via the following modules:

Transmitter PLL Transmitter phase compensation FIFO buffer Byte serializer 8B/10B encoder Serializer (parallel to serial converter) Transmitter output buffer
Transmitter PLL
Each transceiver block has one transmitter PLL, which receives the reference clock and generates the following signals:

High-speed serial clock used by the serializer Slow-speed reference clock used by the receiver Slow-speed clock used by the logic array (divisible by two for double-width mode)
The INCLK clock is the input into the transmitter PLL. There is one INCLK clock per transceiver block. This clock can be fed by either the REFCLKB pin, PLD routing, or the inter-transceiver routing line. See the section "Stratix GX Clocking" on page 36 for more information about the intertransceiver lines. The transmitter PLL in each transceiver block clocks the circuits in the transmit path. The transmitter PLL is also used to train the receiver PLL. If no transmit channels are used in the transceiver block, the transmitter PLL can be turned off. Figure 5 is a block diagram of the transmitter PLL. Figure 5. Transmitter PLL Block Diagram
/m
Note (1)
Clock Driver
High Speed Clock Low Speed Clock
Up Inter Quad Routing (IQ1) Inter Quad Routing (IQ2) Global Clks, IO Bus, Gen Routing INCLK PFD Down Charge Pump + Loop Filter VCO
Dedicated Local REFCLKB
/2
Note to Figure 5:
(1) The divider in the PLL divides by 4, 8, 10, 16, or 20.
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Transceiver Blocks
The transmitter PLL can support up to 3.1875 Mbps. The input clock frequency for -5 and -6 speed grade devices is limited to 650 MHz if designers use the REFCLKB pin or to 325 MHz if designers use the other clock routing resources. For -7 speed grade devices, the maximum input clock frequency is 312.5 MHz with the REFCLKB pin, and the maximum is 156.25 MHz for all other clock routing resources. An optional PLL_LOCKED port is available to indicate whether the transmitter PLL is locked to the reference clock. The transmitter PLL has a programmable loop bandwidth that can be set to low or high. The loop bandwidth parameter can be statically set in the Quartus II software. Table 7 lists the adjustable parameters in the transmitter PLL.
Table 7. Transmitter PLL Specifications Parameter
Input reference frequency range Data rate support Multiplication factor (W) Bandwidth Note to Table 7:
(1) Multiplication factors 2 and 5 can only be achieved with the use of the pre-divider on the REFCLKB pin.
Specifications
25 MHz to 650 MHz 500 Mbps to 3.1875 Gbps 2, 4, 5, 8, 10, 16, or 20 (1) Low, high
Transmitter Phase Compensation FIFO Buffer
The transmitter phase compensation FIFO buffer resides in the transceiver block at the PLD boundary. This FIFO buffer compensates for the phase differences between the transmitter reference clock (inclk) and the PLD interface clock (tx_coreclk). The phase difference between the two clocks must be less than 360. The PLD interface clock must also be frequency locked to the transmitter reference clock. The phase compensation FIFO buffer is four words deep and cannot be bypassed.
Byte Serializer
The byte serializer takes double-width words (16 or 20 bits) from the PLD interface and converts them to a single width word (8 or 10 bits) for use in the transceiver. The transmit data path after the byte serializer is single width (8 or 10 bits). The byte serializer is bypassed when single width mode (8 or 10 bits) is used at the PLD interface.
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8B/10B Encoder
The 8B/10B encoder translates 8-bit wide data + 1 control enable bit into a 10-bit encoded data. The encoded data has a maximum run length of 5. The 8B/10B encoder can be bypassed. Figure 6 diagrams the encoding process. Figure 6. Encoding Process
7 H 6 G 5 F 4 E 3 D 2 C 1 B 0 A + ctrl
8b-10b conversion
j 9
h 8
g 7
f 6
i 5
e 4
d 3
c 2
b 1
a 0
MSB sent last
LSB sent first
Transmit State Machine
The transmit state machine operates in either XAUI mode or in GigE mode, depending on the protocol used. GigE Mode In GigE mode, the transmit state machines convert all idle ordered sets (/K28.5/, /Dx.y/) to either /I1/ or /I2/ ordered sets. /I1/ consists of a negative-ending disparity /K28.5/ (denoted by /K28.5/-) followed by a neutral /D5.6/. /I2/ consists of a positive-ending disparity /K28.5/ (denoted by /K28.5/+) and a negative-ending disparity /D16.2/ (denoted by /D16.2/-). The transmit state machines do not convert any of the ordered sets to match /C1/ or /C2/, which are the configuration ordered sets. (/C1/ and /C2/ are defined by (/K28.5/, /D21.5/) and (/K28.5/, /D2.2/), respectively.) Both the /I1/ and /I2/ ordered sets guarantee a negative-ending disparity after each ordered set. The GigE transmit state machine can be statically disabled in Quartus II, even if the GigE protocol mode is used.
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Transceiver Blocks
XAUI Mode The transmit state machine translates the XAUI XGMII code group to the XAUI PCS code group. Table 8 shows the code conversion.
Table 8. Code Conversion XGMII TXC
0 1 1 1 1 1 1 1
XGMII TXD
00 through FF 07 07 9C FB FD FE
PCS Code-Group
Dxx.y K28.0 or K28.3 or K28.5 K28.5 K28.4 K27.7 K29.7 K30.7
Description
Normal data Idle in ||I|| Idle in ||T|| Sequence Start Terminate Error
Reserved Code Groups See IEEE 802.3 See IEEE 802.3 Reserved Code Reserved Code Groups Groups Other value K30.7 Invalid XGMII character
1
The XAUI PCS idle code groups, /K28.0/ (/R/) and /K28.5/ (/K/), are automatically randomized based on a PRBS7 pattern with an x7+x6+1 polynomial. The /K28.3/ (/A/) code group is automatically generated between 16 and 31 idle code groups. The idle randomization on the /A/, /K/, and /R/ code groups are done automatically by the transmit state machine.
Serializer (Parallel-to-Serial Converter)
The serializer converts the parallel 8-bit or 10-bit data into a serial stream, transmitting the LSB first. The serialized stream is then fed to the transmit buffer. Figure 7 is a diagram of the serializer.
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Figure 7. Serializer
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Low-speed parallel clock High-speed serial clock D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Serial data out (to output buffer)
10
Transmit Buffer
The Stratix GX transceiver buffers support the 1.5-V pseudo current mode logic (PCML) I/O standard at a rate up to 3.1875 Gbps, across up to 40 inches of FR4 trace, and across 2 connectors. Additional I/O standards, LVDS, 3.3-V PCML, LVPECL, can be supported when AC coupled. The common mode of the Output Driver is 750 mV. The output buffer, as shown in Figure 8, consists of a programmable output driver and a programmable pre-emphasis circuit.
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Transceiver Blocks
Figure 8. Output Buffer
Serializer
Output Buffer
Programmable Pre-Emphasis Programmable Output Driver
Programmable Termination
Output Pins
Programmable Output Driver The programmable output driver can be set to drive out 400 to 1,600 mV. Table 9 shows the available settings for each termination value. The VOD can be dynamically or statically set. The output driver requires either internal or external termination at the source.
Table 9. Programmable VOD (Differential) Termination Setting ()
100 120 150 Note to Table 9:
(1)
Note (1) VO D Setting (mV)
400, 800, 1000, 1200, 1400, 1600 480, 960, 1200, 1440 600, 1200, 1500
VOD differential is measured as VA - VB (see Figure 9).
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Figure 9. VOD Differential
Single-Ended Waveform VA VOD VB Differential Waveform VOCM + +VOD VOCM VOD (Differential) = VA - VB VOD (Differential) - VOD VOCM - VA - VB 2 VA - VB 2
Programmable Pre-Emphasis The programmable pre-emphasis module controls the output driver to boost the high frequency components, to compensate for losses in the transmission medium, as shown in Figure 10. The pre-emphasis can be dynamically or statically set. There are five possible pre-emphasis settings (1 through 5), with 5 being the highest and 0 being no pre-emphasis. Figure 10. Programmable Pre-Emphasis Model
VPP VS VCM VS(p-p) VPP(p-p)
Bit Time
Bit Time
Pre-emphasis percentage is defined as VPP/VS - 1, where VPP is the differential emphasized voltage (peak-to-peak) and VS is the differential steady-state voltage (peak-to-peak).
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Transceiver Blocks
Programmable Transmitter Termination The programmable termination can be statically set in the Quartus II software. The values are 100 , 120 , 150 , and off. Figure 11 shows the setup for programmable termination. Figure 11. Programmable Transmitter Termination
VCM Programmable Output Driver
50, 60, or 75
Receiver Path
This section describes the data path through the Stratix GX receiver (refer to Figure 4 on page 11). Data travels through the Stratix GX receiver via the following modules:

Input buffer Clock Recovery Unit (CRU) Deserializer Pattern detector and word aligner Rate matcher and channel aligner 8B/10B decoder Receiver logic array interface
Receiver Input Buffer
The Stratix GX receiver input buffer supports the 1.5-V PCML I/O standard at a rate up to 3.1875 Gbps. Additional I/O standards, LVDS, 3.3-V PCML, and LVPECL can be supported when AC coupled. The common mode of the input buffer is 1.1 V. The receiver can support Stratix GX-to-Stratix GX DC coupling. Figure 12 shows a diagram of the receiver input buffer, which contains:

Programmable termination Programmable equalizer
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Figure 12. Receiver Input Buffer
Programmable Termination Input Pins Programmable Equalizer Differential Input Buffer
Programmable Termination The programmable termination can be statically set in the Quartus II software. Figure 13 shows the setup for programmable receiver termination. Figure 13. Programmable Receiver Termination
Differential Input Buffer VCM
50, 60, or 75
50, 60, or 75
If external termination is used, then the receiver must be externally terminated and biased to 1.1 V. Figure 14 shows an example of an external termination/biasing circuit.
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Transceiver Blocks
Figure 14. External Termination & Biasing Circuit
Receiver External Termination and Biasing Stratix GX Device
50/60/75- Termination Resistance
VDD
R1 C1
Receiver
R1/R2 = 1K VDD x {R2/(R1 + R 2)} = 1.1 V RXIP R2 RXIN
Receiver External Termination and Biasing Transmission Line
Programmable Equalizer
The programmable equalizer module boosts the high frequency components of the incoming signal to compensate for losses in the transmission medium. There are five possible equalization settings (0, 1, 2, 3, 4) to compensate for 0", 10", 20", 30", and 40" of FR4 trace. These settings should be interpreted loosely. The programmable equalizer can be set dynamically or statically.
Receiver PLL & CRU
Each transceiver block has four receiver PLLs and CRUs, each of which is dedicated to a receive channel. If the receive channel associated with a particular receiver PLL or CRU is not used, then the receiver PLL or CRU is powered down for the channel. Figure 15 is a diagram of the receiver PLL and CRU circuits.
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Figure 15. Receiver PLL & CRU Circuit
Receiver PLL
/ m (1)
rx_locked
PFD Low-Speed TX_PLL_CLK Inter Transceiver Routing (IQ1) RX CRUCLK Global Clks, IO Bus, Gen Routing up down up down Charge Pump and Loop Filter VCO
Dedicated Local REFCLKB
/2
rx_locktorefclk rx_locktodata RX_IN CRU
rx_freqlocked[] rx_riv[ ] High-speed RCVD_CLK Low-speed RCVD_CLK
Note to Figure 15:
(1) m = 8, 10 16, or 20.
The receiver PLLs and CRUs are capable of supporting up to 3.1875 Gbps. The input clock frequency for -5 and -6 speed grade devices is limited to 650 MHz if designers use the REFCLKB pin or 325 MHz if designers use the other clock routing resources. The maximum input clock frequency for -7 speed grade devices is 312.5 MHz if designers use the REFCLKB pin or 156.25 MHz with the other clock routing resources. An optional RX_LOCKED port (active low signal) is available to indicate whether the PLL is locked to the reference clock. The receiver PLL has a programmable loop bandwidth, which can be set to low, medium, or high. The loop bandwidth parameter can be statically set by the Quartus II software.
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Transceiver Blocks
Table 10 lists the adjustable parameters of the receiver PLL and CRU. All the parameters listed are statically programmable in the Quartus II software.
Table 10. Receiver PLL & CRU Adjustable Parameters Parameter
Input reference frequency range Data rate support Multiplication factor (W) PPM detector Bandwidth Run length detector
Specifications
25 MHz to 650 MHz 500 Mbps to 3.1875 Gbps 2, 4, 5, 8, 10, 16, or 20 (1) 125, 250, 500, 1,000 Low, medium, high 10-bit or 20-bit mode: 5 to 160 in steps of 5 8-bit or 16-bit mode: 4 to 128 in steps of 4
Note to Table 10:
(1) Multiplication factors 2, 4, and 5 can only be achieved with the use of the predivider on the REFCLKB port or if the CRU is trained with the low speed clock from the transmitter PLL.
The CRU has a built-in switchover circuit to select whether the voltage-controlled oscillator of the PLL is trained by the reference clock or the data. The optional port rx_freqlocked can be used to monitor when the CRU is in locked to data mode. In the automatic mode, the following conditions must be met for the CRU to switch from locked to reference to locked to data mode:
The CRU PLL is within the prescribed PPM frequency threshold setting (125 PPM, 250 PPM, 500 PPM, 1,000 PPM) of the CRU reference clock. The reference clock and CRU PLL output are phase matched (phases are within .08 UI).
The automatic switchover circuit can be overridden by using the optional ports rx_lockedtorefclk and rx_locktodata. Table 11 shows the possible combinations of these two signals. If the rx_lockedtorefclk and rx_locktodata ports are not used, the default is auto mode.
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Stratix GX FPGA Family
Table 11. Possible Combinations of rx_lockedtorefclk & rx_locktodata rx_locktodata
0 0 1
rx_lockedtorefclk
0 1 x
VCO (lock to mode)
Auto Reference CLK DATA
Deserializer (Serial-to-Parallel Converter)
The deserializer converts the serial stream into a parallel 8- or 10-bit data bus. The deserializer receives the least significant bit first. Figure 16 is a diagram of the deserializer. Figure 16. Deserializer
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
10
High-speed serial clock Low-speed parallel clock
Word Aligner
The word aligner aligns the incoming data based on the specific byte boundaries. The word aligner has three customizable modes of operation: bit-slip mode, 16-bit mode, and 10-bit mode, the last of which is available for the basic and SONET modes. The word aligner also has two non-customizable modes of operation, which are the XAUI and GigE modes.
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Transceiver Blocks
Figure 17 shows the word aligner in bit-slip mode. Figure 17. Word Aligner in Bit-Slip Mode
Word Aligner
Patterm Detector
Manual Alignment Mode
Bit-Slip Mode
10-Bit Mode
16-Bit Mode
7-Bit Mode
A1A2 Mode
A1A1A2A2 Mode
In the bit-slip mode, the byte boundary can be modified by a barrel shifter to slip the byte boundary one bit at a time via a user-controlled bit-slip port. The bit-slip mode supports both 8-bit and 10-bit datapaths operating in a single or double-width mode. The pattern detector is active in the bit-slip mode, and it will detect the user-defined pattern that is specified in the MegaWizard(R) Plug-In Manager. The bit-slip mode is available only in basic mode and SONET mode. Figure 18 shows the word aligner in 16-bit mode.
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Stratix GX FPGA Family
Figure 18. Word Aligner in 16-Bit Mode
Word Aligner
Pattern Detector
Manual Alignment Mode
16-Bit Mode
16-Bit Mode
A1A2 Mode
A1A1A2A2 Mode A1A2 Mode A1A1A2A2 Mode
In the 16-bit mode, the word aligner and pattern detector automatically aligns and detects a user-defined 16-bit alignment pattern. This pattern can be in the format of A1A2 or A1A1A2A2 (for the SONET protocol). The re-alignment of the byte boundary can be done via a user-controlled port. The 16-bit mode supports only the 8-bit data path in a single-width or double-width mode. The 16-bit mode is available only for the basic mode and SONET mode. The A1A1A2A2 word alignment pattern option is available only for the SONET mode and cannot be used in the basic mode. Figure 19 shows the word aligner in 10-bit mode.
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Transceiver Blocks
Figure 19. Word Aligner in 10-Bit Mode
Word Aligner
Pattern Detector
Manual Alignment Mode
10-Bit Mode
7-Bit Mode
10-Bit Mode
In the 10-bit mode, the word aligner automatically aligns the user's predefined 10-bit alignment pattern. The pattern detector can detect the full 10-bit pattern or only the lower seven bits of the pattern. The word aligner and pattern detector detect both the positive and the negative disparity of the pattern. A user-controlled enable port is available for the word aligner. The 10-bit mode is available only for the basic mode. Figure 20 shows the word aligner in XAUI mode.
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Stratix GX FPGA Family
Figure 20. Word Aligner in XAUI Mode
Word Aligner
Synchronization State Machines
GigE Mode
XAUI Mode
In the XAUI and GigE modes, the word alignment is controlled by a state machine that adheres to the IEEE 802.3ae standard for XAUI and the IEEE 802.3 standard for GigE. The alignment pattern is predefined to be a /K28.5/ code group. The XAUI mode is available only for the XAUI protocol, and the GigE mode is available only for the GigE protocol.
Channel Aligner
The channel aligner is available only in XAUI mode and bonds all four channels within a transceiver. The channel aligner adheres to the IEEE 802.3ae, clause 48 specification for channel bonding. The channel aligner is a 16-word deep FIFO buffer with a state machine overlooking the channel bonding process. The state machine looks for an /A/ (/K28.3/) in each channel and aligns all the /A/s in the transceiver. When four columns of /A/ (denoted by //A//) are detected, the rx_channelalign port goes high, signifying that all the channels in the transceiver have been bonded. The reception of four consecutive misaligned /A/s restarts the channel alignment sequence and de-asserts rx_channelalign. Figure 21 shows misaligned channels before the channel aligner and the channel alignment after the channel aligner.
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Transceiver Blocks
Figure 21. Before & After the Channel Aligner
Lane 0 K Lane 0 K R A K R R K K R K R
K
K
R
A
K
R
R
K
K
R
K
R
Lane 0
K
K
R
A
K
R
R
K
K
R
K
R
Lane 0
K
K
R
A
K
R
R
K
K
R
K
R
Lane 0
K
K
R
A
K
R
R
K
K
R
K
R
Lane 0
K
K
R
A
K
R
R
K
K
R
K
R
Lane 0
K
K
R
A
K
R
R
K
K
R
K
R
Lane 0
K
K
R
A
K
R
R
K
K
R
K
R
Rate Matcher
The rate matcher, which is available only in XAUI and GigE modes, consists of a 12-word deep FIFO buffer and a FIFO controller. The rate matcher is bypassed when the device is not in XAUI or GigE mode. In a multi-crystal environment, the rate matcher compensates for up to a 100-ppm difference between the source and receiver clocks. GigE Mode In the GigE mode, the rate matcher adheres to the specifications in clause 36 of the IEEE 802.3 documentation, for idle additions or removals. The rate matcher performs clock compensation only on /I2/ ordered sets, composing a /K28.5/+ followed by a /D16.2/-. The rate matcher does not perform a clock compensation on any other ordered set combinations. An /I2/ is added or deleted automatically based on the number of words in the FIFO buffer. A 9'h19C is given at the control and data ports when the FIFO is in an overflow or underflow condition.
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XAUI Mode In XAUI mode, the rate matcher adheres to clause 48 of the IEEE 802.3ae specification for clock rate compensation. The rate matcher performs clock compensation on columns of /R/ (/K28.0/), denoted by //R//. An //R// is added or deleted automatically based on the number of words in the FIFO buffer.
8B/10B Decoder
The 8B/10B decoder converts the 10-bit encoded code group into 8-bit data and 1 control bit. The 8B/10B decoder can be bypassed. The following is a diagram of the conversion from a 10-bit encoded code group into 8-bit data + 1-bit control. Figure 22. 8B/10B Decoder Conversion
j 9 h 8 g 7 f 6 i 5 e 4 d 3 c 2 b 1 a 0
MSB received last 8b-10b conversion
LSB received first
Parallel data
7 H
6 G
5 F
4 E
3 D
2 C
1 B
0 A
+
ctrl
There are two optional error status ports available in the 8B/10B decoder, rx_errdetect and rx_disperr. Table 12 shows the values of the ports from a given error. These status signals are aligned with the code group in which the error occurred.
Table 12. Error Signal Values Types of Errors
No errors Invalid code groups Disparity errors
rx_errdetect
1'b0 1'b1 1'b1
rx_disperr
1'b0 1'b0 1'b1
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Transceiver Blocks
Receiver State Machine
The receiver state machine operates in GigE and XAUI modes. In GigE mode, the receiver state machine replaces invalid code groups with 9'h1FE. In XAUI mode, the receiver state machine translates the XAUI PCS code group to the XAUI XGMII code group. Table 13 shows the code conversion. The conversion adheres to the IEEE 802.3ae specification.
Table 13. Code Conversion XGMII RXC
0 1 1 1 1 1 1 1 1 07 07 9C FB FD FE FE See IEEE 802.3 reserved code groups
XGMII RXD
00 through FF Dxx.y
PCS code-group
K28.0 or K28.3 or K28.5 K28.5 K28.4 K27.7 K29.7 K30.7 Invalid code group See IEEE 802.3 reserved code groups Idle in ||I||
Description
Normal Data
Idle in ||T|| Sequence Start Terminate Error Invalid XGMII character Reserved code groups
Byte Deserializer
The byte deserializer takes a single width word (8 or 10 bits) from the transceiver logic and converts it into double-width words (16 or 20 bits) to the phase compensation FIFO buffer. The byte deserializer is bypassed when single width mode (8 or 10 bits) is used at the PLD interface.
Phase Compensation FIFO Buffer
The receiver phase compensation FIFO buffer resides in the transceiver block at the programmable logic device (PLD) boundary. This buffer compensates for the phase difference between the recovered clock within the transceiver and the recovered clock after it has transferred to the PLD core. The phase compensation FIFO buffer is four words deep and cannot be bypassed.
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Stratix GX FPGA Family
Loopback Modes
The Stratix GX transceiver has built-in loopback modes to aid in debug and testing. The loopback modes are set in the Stratix GX MegaWizard Plug-In Manager in the Quartus II software. Only one loopback mode can be set at any single instance of the transceiver block. The loopback mode applies to all used channels in a transceiver block. The available loopback modes are:

Serial loopback Parallel loopback Reverse serial loopback
Serial Loopback
Serial loopback exercises all the transceiver logic except for the output buffer and input buffer. The loopback function is dynamically switchable through the rx_slpbk port on a channel by channel basis. The VOD of the output is limited to 400 mV when the serial loopback option is selected. Figure 23 shows the data path in serial loopback mode. Figure 23. Data Path in Serial Loopback Mode
BIST PRBS Verifier Deserializer Word Aligner BIST Incremental Verifier Rate Matcher 8B/10B Decoder
Phase Compensation FIFO
Channel Aligner
Clock Recovery Unit
Byte Deserializer
Serializer
8B/10B Encoder BIST PRBS Generator
Byte Serializer
Phase Compensation FIFO
BIST Generator
Active Path Non-active Path
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Transceiver Blocks
Parallel Loopback
The parallel loopback mode exercises the digital logic portion of the transceiver data path. The analog portions are not use in the loopback path. The received data is not retimed. Figure 24 shows the data path in parallel loopback mode. This option is not dynamically switchable. Reception of an external signal is not possible in this mode. Figure 24. Data Path in Parallel Loopback Mode
BIST PRBS Verifier Deserializer Word Aligner BIST Incremental Verifier Rate Matcher 8B/10B Decoder
Phase Compensation FIFO
Channel Aligner
Clock Recovery Unit
Byte Deserializer
Serializer
8B/10B Encoder BIST PRBS Generator
Byte Serializer
Phase Compensation FIFO
BIST Generator
Active Path Non-active Path
Reverse Serial Loopback
The reverse serial loopback exercises the analog portion of the transceiver. This loopback mode is dynamically switchable through the tx_srlpbk port on a channel by channel basis. Asserting rxanalogreset in reverse serial loopback mode powers down the receiver buffer and CRU, preventing data loopback. Figure 25 shows the data path in reverse serial loopback mode.
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Stratix GX FPGA Family
Figure 25. Data Path in Reverse Serial Loopback Mode
BIST PRBS Verifier Deserializer Word Aligner BIST Incremental Verifier Rate Matcher 8B/10B Decoder
Phase Compensation FIFO
Channel Aligner
Clock Recovery Unit
Byte Deserializer
Serializer
8B/10B Encoder BIST PRBS Generator
Byte Serializer
Phase Compensation FIFO
Active Path Non-active Path
BIST Generator
BIST (Built-In Self Test)
The Stratix GX transceiver has built-in self test modes to aid in debug and testing. The BIST modes are set in the Stratix GX MegaWizard Plug-In Manager in the Quartus II software. Only one BIST mode can be set for any single instance of the transceiver block. The BIST mode applies to all channels used in a transceiver. The following is a list of the available BIST modes:

PRBS generator and verifier Incremental mode generator and verifier High-frequency generator Low-frequency generator Mixed-frequency generator
Figures 26 and 27 are diagrams of the BIST PRBS data path and the BIST incremental data path, respectively.
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Transceiver Blocks
Figure 26. BIST PRBS Data Path
BIST PRBS Verifier Deserializer Word Aligner BIST Incremental Verifier Rate Matcher 8B/10B Decoder
Phase Compensation FIFO
Channel Aligner
Clock Recovery Unit
Byte Deserializer
Serializer
8B/10B Encoder BIST PRBS Generator
Byte Serializer
Phase Compensation FIFO
BIST Generator
Active Path Non-active Path
Figure 27. BIST Incremental Data Path
BIST PRBS Verifier Deserializer Word Aligner BIST Incremental Verifier Rate Matcher 8B/10B Decoder
Phase Compensation FIFO
Channel Aligner
Clock Recovery Unit
Byte Deserializer
Serializer
8B/10B Encoder BIST PRBS Generator
Byte Serializer
Phase Compensation FIFO
BIST Generator
Active Path Non-active Path
Table 14 shows the BIST data output and verifier alignment pattern.
Table 14. BIST Data Output & Verifier Alignment Pattern (Part 1 of 2) BIST Mode
PRBS 8-bit PRBS 10-bit 28 - 1 210 - 1
Output
Polynomials
x8 + x7 + x5 + x3 + 1 x10 + x7 + 1
Verifier Word Alignment Pattern
1000000011111111 1111111111
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Stratix GX FPGA Family
Table 14. BIST Data Output & Verifier Alignment Pattern (Part 2 of 2) BIST Mode
PRBS 16-bit PRBS 20-bit Incremental 10-bit 28 - 1 210 - 1 K28.5, K27.7, Data (00-FF incremental), K28.0, K28.1, K28.2, K28.3, K28.4, K28.6, K28.7, K23.7, K30.7, K29.7 (1) K28.5, K27.7, Data (00-FF incremental), K28.0, K28.1, K28.2, K28.3, K28.4, K28.6, K28.7, K23.7, K30.7, K29.7 (1) 1010101010 0011111000 0011111010 or 1100000101
Output
Polynomials
x8 + x7 + x5 + x3 + 1 x10 + x7 + 1
Verifier Word Alignment Pattern
1000000011111111 1111111111 0101111100 (K28.5)
Incremental 20-bit
0101111100 (K28.5)
High frequency Low frequency Mixed frequency Note to Table 14:
(1)
This output repeats.
Stratix GX Clocking
The Stratix GX global clock can be driven by certain REFCLKB pins, all transmitter PLL outputs, and all receiver PLL outputs. The REFCLKB pins (except for transceiver block 0 and transceiver block 4) can drive intertransceiver and global clock lines as well as feed the transmitter and receiver PLLs. The output of the transmitter PLL can only feed global clock lines and the reference clock port of the receiver PLL. Figures 28 and 29 are diagrams of the Inter-Transceiver line connections as well as the global clock connections for the EP1SGX25F and EP1SGX40G devices. For devices with fewer transceivers, ignore the information about the unavailable transceiver blocks.
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Transceiver Blocks
Figure 28. EP1SGX25F Device Inter-Transceiver & Global Clock Connections
IQ0 IQ1 IQ2 Transceiver Block 0
IQ0 IQ1 Global Clocks, I/O Bus, General Routing
Note (1)
Transmitter PLL /2 4 Receiver PLLs (2)
refclkb
IQ2
Global Clocks, I/O Bus, General Routing
Transceiver Block 1
IQ0 IQ1 Global Clocks, I/O Bus, General Routing
Transmitter PLL /2 4 Receiver PLLs (2)
refclkb
IQ2
Global Clocks, I/O Bus, General Routing
PLD Global Clocks 16
Transceiver Block 2
IQ0 IQ1 Global Clocks, I/O Bus, General Routing
Transmitter PLL /2 4 Receiver PLLs (2)
refclkb
IQ2
Global Clocks, I/O Bus, General Routing
Transceiver Block 3
IQ0 IQ1 Global Clocks, I/O Bus, General Routing
Transmitter PLL /2 4 Receiver PLLs (2)
refclkb
IQ2
Global Clocks, I/O Bus, General Routing
Notes to Figure 28:
(1) (2) IQ lines are inter-transceiver block lines. There are four receiver PLLs in each transceiver block.
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Figure 29. EP1SGX40G Device Inter-Transceiver & Global Clock Connections
IQ0 IQ1 IQ2 Transceiver Block 0
IQ0 IQ1 Global Clocks, I/O Bus, General Routing
Note (1)
Transmitter PLL /2 4 Receiver PLLs (2)
refclkb
IQ2
Global Clocks, I/O Bus, General Routing
Transceiver Block 1
IQ0 IQ1 Global Clocks, I/O Bus, General Routing
Transmitter PLL /2 4 Receiver PLLs (2) 16 PLD Global Clocks
refclkb
IQ2
Global Clocks, I/O Bus, General Routing
Transceiver Block 4
IQ0 IQ1 Global Clocks, I/O Bus, General Routing
Transmitter PLL /2 4 Receiver PLLs (2)
refclkb
IQ2 Global Clocks, I/O Bus, General Routing
Transceiver Block 2
IQ0 IQ1 Global Clocks, I/O Bus, General Routing
Transmitter PLL /2 4 Receiver PLLs (2)
refclkb
IQ2
Global Clocks, I/O Bus, General Routing
Transceiver Block 3
IQ0 IQ1 Global Clocks, I/O Bus, General Routing
Transmitter PLL /2 4 Receiver PLLs (2)
refclkb
IQ2
Global Clocks, I/O Bus, General Routing
Notes to Figure 29:
(1) (2) IQ lines are inter-transceiver block lines. There are four receiver PLLs in each transceiver block.
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Transceiver Blocks
The receiver PLL can also drive the fast regional, regional clocks, and local routing adjacent to the associated transceiver block. Figures 30 through 33 show which fast regional and regional clock resource can be used by the recovered clock. In the EP1SGX25 device, the receiver PLL recovered clocks from transceiver blocks 0 and 1 drive RCLK[1..0] while transceiver blocks 2 and 3 drive RCLK[7..6]. The regional clocks feed logic in their associated regions. Figure 30. EP1SGX25 Receiver PLL Recovered Clock to Regional Clock Connection
PLD Stratix GX Transceiver Blocks Block 0
RCLK[11..10]
Block 1
Block 2
RCLK[9..8]
Block 3
In addition, the receiver PLL's recovered clocks can drive fast regional lines (FCLK) as shown Figure 31. The fast regional clocks can feed logic in their associated regions.
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Figure 31. EP1SGX25 Receiver PLL Recovered Clock to Fast Regional Clock Connection
PLD
FCLK[1..0]
Stratix GX Transceiver Blocks Block 0
Block 1
Block 2
Block 3
FCLK[1..0]
In the EP1SGX40 device, the receiver PLL recovered clocks from transceivers 0 and 1 drive RCLK[1..0] while transceivers 2, 3, and 4 drive RCLK[7..6]. The regional clocks feed logic in their associated regions.
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Transceiver Blocks
Figure 32. EP1SGX40 Receiver PLL Recovered Clock to Regional Clock Connection
PLD Stratix GX Transceiver Blocks Block 0
RCLK[11..10]
Block 1
Block 4
Block 2
RCLK[9..8]
Block 3
Figure 33 shows the possible recovered clock connection to the fast regional clock resource. The fast regional clocks can drive logic in their associated regions.
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Stratix GX FPGA Family
Figure 33. EP1SGX40 Receiver PLL Recovered Clock to Fast Regional Clock Connection
Stratix GX PLD
FCLK[1..0] Transceiver Blocks
Block 0
Block 1
Block 4
Block 2
Block 3
FCLK[1..0]
Table 15 summarizes the possible clocking connections for the transceivers.
Table 15. Possible Clocking Connections for Transceivers (Part 1 of 2) Destination Source
REFCLKB Transmitter PLL Receiver PLL GCLK RCLK FCLK v v v v v v
Transmitter PLL
v
Receiver PLL
v v
GCLK
v (1) v v
RCLK
v v v
FCLK
IQ Lines
v (1)
v v
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Other Transceiver Features
Table 15. Possible Clocking Connections for Transceivers (Part 2 of 2) Destination Source
IQ lines Notes to Table 15:
(1) (2) REFCLKB from transceiver block 0 and transceiver block 4 does not drive the inter-transceiver lines or the GCLK lines. Inter-transceiver line 0 and inter-transceiver line 1 drive the transmitter PLL, while inter-transceiver line 2 drives the receiver PLLs.
Transmitter PLL
v (2)
Receiver PLL
v (2)
GCLK
RCLK
FCLK
IQ Lines
Other Transceiver Features
Other important features of the Stratix GX transceivers are the power down and reset capabilities, the external voltage reference and bias circuitry, and hot swapping.
Individual Power-Down & Reset for the Transmitter & Receiver
Stratix GX transceivers offer a power saving advantage with their ability to shut off functions that are not needed. The device can individually reset the receiver and transmitter blocks and the PLLs. The Stratix GX device can either globally power down and reset the transmitter and receiver channels or do each channel separately. Table 16 shows the connectivity between the reset signals and the Stratix GX logical blocks.
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Stratix GX FPGA Family
Power-down functions are static, in other words., they are implemented upon device configuration and programmed, through the Quartus II software, to static values. Resets can be static as well as dynamic inputs coming from the logic array or pins.
Table 16. Reset Signal Map to Stratix GX Blocks Transmitter Phase Compensation FIFO Module/ Byte Serializer
Transmitter XAUI State Machine
Receiver Deskew FIFO Module
Reset Signal
Receiver Phase Comp FIFO Module/ Byte Deserializer
Receiver XAUI State Machine
Transmitter 8B/10B Encoder
Transmitter Analog Circuits
Transmitter Analog Circuits
Receiver 8B/10B Decoder
rxdigitalreset rxanalogreset txdigitalreset v v pll_areset pllenable
v v v v v v v v v v v v v v v v v v v v v
v
v
v
v
v v
v
v v
v v
v v
v v
v v
v v
v v
v v
v v
v v
Voltage Reference Capabilities
Stratix GX transceivers provide voltage reference and bias circuitry. To set-up internal bias for controlling the transmitter output drivers' voltage swing--as well as to provide voltage/current biasing for other analog circuitry--the internal bandgap voltage reference at 0.7 V is used. To provide bias for internal pull-up PMOS resistors for I/O termination at the serial interface of receiver and transmitter channels (independent of power supply drift, process changes, or temperature variation) an external resistor, which is connected to the external low voltage power
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Receiver Analog Circuits
Receiver Rate Matcher
Receiver Word Aligner
Transmitter Serializer
Receiver Deserializer
Receiver PLL / CRU
BIST Generators
Transmitter PLL
BIST Verifiers
Applications & Protocols Supported with Stratix GX Devices
supply, is accurately tracked by the internal bias circuit. Moreover, the reference voltage and internal resistor bias current is generated and replicated to the analog circuitry in each channel.
Hot-Socketing Capabilities
Each Stratix GX device is capable of hot-socketing. Because Stratix GX devices can be used in a mixed-voltage environment, they have been designed specifically to tolerate any possible power-up sequence. Signals can be driven into Stratix GX devices before and during power-up without damaging the device. Once operating conditions are reached and the device is configured, Stratix GX devices operate as specified by the designer. This feature provides the Stratix GX transceiver line card behavior, so designers can insert it into the system without powering the system down, offering more flexibility.
Applications & Protocols Supported with Stratix GX Devices
Each Stratix GX transceiver block is designed to operate at any serial bit rate from 500 Mbps to 3.1875 Gbps per channel. The wide, data rate range allows Stratix GX transceivers to support a wide variety of standard and future protocols such as 10-Gigabit Ethernet XAUI, InfiniBand, Fibre Channel, and Serial RapidIO. Stratix GX devices are ideal for many highspeed communication applications such as high-speed backplanes, chipto-chip bridges, and high-speed serial communications standards support.
Stratix GX Example Application Support
Stratix GX devices can be used for many applications, including:

Backplanes for traffic management and quality of service (QOS) Switch fabric applications for complete set for backplane and switch fabric transceivers Chip-to-chip applications such as: 10 Gigabit Ethernet XAUI to XGMII bridge, 10 Gigabit Ethernet XGMII to POS-PHY4 bridge, POS-PHY4 to NPSI bridge, or NPSI to backplane bridge
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High-Speed Serial Bus Protocols
With wide, serial data rate range, Stratix GX devices can support multiple, high-speed serial bus protocols. Table 17 shows some of the protocols that Stratix GX devices can support.
Table 17. High-Speed Serial Bus Protocols Bus Transfer Protocol
SONET backplane 10 Gigabit Ethernet XAUI 10 Gigabit fibre channel InfiniBand Fibre channel (1G, 2G) Serial RapidIOTM PCI Express SMPTE 292M 2.488 3.125 3.1875 2.5 1.0625, 2.125 1.25, 2.5, 3.125 2.5 1.485
Stratix GX (Gbps) (Supports up to 3.1875 Gbps)
SourceSynchronous Signaling with DPA
Expansion in the telecommunications market and growth in Internet use requires systems to move more data faster than ever. To meet this demand, system designers rely on solutions such as differential signaling and emerging high-speed interface standards including RapidIO, POS-PHY 4, SFI-4, or XSBI. These new protocols support differential data rates up to 1 Gbps and higher. At these high data rates, it becomes more challenging to manage the skew between the clock and data signals. One solution to this challenge is to use CDR to eliminate skew between data channels and clock signals. Another potential solution, DPA, is beginning to be incorporated into some of these protocols. The source-synchronous high-speed interface in Stratix GX devices is a dedicated circuit embedded into the PLD allowing for high-speed communications. The High-Speed Differential I/O Interfaces in Stratix Devices chapter of the Stratix Handbook, Volume 2 provides information on the high-speed I/O standard features and functions of the Stratix GX device.
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Source-Synchronous Signaling with DPA
Stratix GX I/O Banks
Stratix GX devices contain 17 I/O banks, as shown in Figure 1 on page 5. I/O banks one and two support high-speed LVDS, LVPECL, and 3.3-V PCML inputs and outputs. These two banks also incorporate an embedded dynamic phase aligner within the source-synchronous interface (see Figure 41 on page 56). The dynamic phase aligner corrects for the phase difference between the clock and data lines caused by skew. The dynamic phase aligner operates automatically and continuously without requiring a fixed training pattern, and allows the source-synchronous circuitry to capture data correctly regardless of the channel-to-clock skew.
Principles of SERDES Operation
Stratix GX devices support source-synchronous differential signaling up to 1 Gbps in DPA mode, and up to 840 Mbps in non-DPA mode. Serial data is transmitted and received along with a low-frequency clock. The PLL can multiply the incoming low-frequency clock by a factor of 1 to 10. The SERDES factor J can be 8 or 10 for the DPA mode, or 4, 7, 8, or 10 for all other modes. The SERDES factor does not have to equal the clock multiplication value. The x1 and x2 operation is also possible by bypassing the SERDES. The SERDES DPA cannot support x1, x2, or x4 natively. On the receiver side, the high-frequency clock generated by the PLL shifts the serial data through a shift register (also called deserializer). The parallel data is clocked out to the logic array synchronized with the lowfrequency clock. On the transmitter side, the parallel data from the logic array is first clocked into a parallel-in, serial-out shift register synchronized with the low-frequency clock and then transmitted out by the output buffers. There are two dedicated fast PLLs each in EP1SGX10 to EP1SGX25 devices, and four in EP1SGX40 devices. These PLLs are used for the SERDES operations as well as general-purpose use.
Stratix GX Differential I/O Receiver Operation (Non-DPA Mode)
Designers can configure any of the Stratix GX source synchronous differential input channels as a receiver channel (see Figure 34). The differential receiver deserializes the incoming high-speed data. The input shift register continuously clocks the incoming data on the negative transition of the high-frequency clock generated by the PLL clock (xW).
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The data in the serial shift register is shifted into a parallel register by the RXLOADEN signal generated by the fast PLL counter circuitry on the third falling edge of the high-frequency clock. However, designers can select which falling edge of the high frequency clock loads the data into the parallel register, using the data-realignment circuit. In normal mode, the enable signal RXLOADEN loads the parallel data into the next parallel register on the second rising edge of the low-frequency clock. Designers can also load data to the parallel register through the TXLOADEN signal when using the data-realignment circuit. Figure 34 shows the block diagram of a single SERDES receiver channel. Figure 35 shows the timing relationship between the data and clocks in Stratix GX devices in x10 mode. W is the low-frequency multiplier and J is the data parallelization division factor. Figure 34. Stratix GX High-Speed Interface Deserialized in x10 Mode
Receiver Circuit Serial Shift Registers Parallel Registers Parallel Registers
RXIN+ RXIN-
PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8 PD9
PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8 PD9
PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8 PD9
Stratix GX Logic Array
xW RXCLKIN+ RXCLKIN- Fast RXLOADEN PLL (2) TXLOADEN
xW/J (1)
Notes to Figure 34:
(1) W = 1, 2, 4, 7, 8, or 10. J = 4, 7, 8, or 10 for non-DPA (J = 8 or 10 for DPA). W does not have to equal J. When J = 1 or 2, the deserializer is bypassed. When J = 2, the device uses DDRIO registers. This figure does not show additional circuitry for clock or data manipulation.
(2)
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Figure 35. Receiver Timing Diagram
Internal x1 clock Internal x10 clock RXLOADEN Receiver data input
n-1
n-0
9
8
7
6
5
4
3
2
1
0
Stratix GX Differential I/O Transmitter Operation
Designers can configure any of the Stratix GX differential output channels as a transmitter channel. The differential transmitter is used to serialize outbound parallel data. The logic array sends parallel data to the SERDES transmitter circuit when the TXLOADEN signal is asserted. This signal is generated by the high-speed counter circuitry of the logic array low-frequency clock's rising edge. The data is then transferred from the parallel register into the serial shift register by the TXLOADEN signal on the third rising edge of the high-frequency clock. Figure 36 shows the block diagram of a single SERDES transmitter channel and Figure 37 shows the timing relationship between the data and clocks in Stratix GX devices in x10 mode. W is the low-frequency multiplier and J is the data parallelization division factor.
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Figure 36. Stratix GX High-Speed Interface Serialized in x10 Mode
Transmitter Circuit Parallel Register Serial Register
Stratix GX Logic Array
PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0
PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0
TXOUT+ TXOUT-
xW Fast PLL TXLOADEN
Figure 37. Transmitter Timing Diagram
Internal x1 clock Internal x10 clock TXLOADEN Receiver data input
n-1
n-0
9
8
7
6
5
4
3
2
1
0
DPA Block Overview
Each Stratix GX receiver channel features a DPA block. The block contains a dynamic phase selector for phase detection and selection, a SERDES, a synchronizer, and a data realigner circuit. Designers can bypass the dynamic phase aligner without affecting the basic source-synchronous operation of the channel by using a separate deserializer shown in Figure 38.
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Source-Synchronous Signaling with DPA
The dynamic phase aligner uses both the source clock and the serial data. The dynamic phase aligner automatically and continuously tracks fluctuations caused by system variations and self-adjusts to eliminate the phase skew between the multiplied clock and the serial data. Figure 38 shows the relationship between Stratix GX source-synchronous circuitry and the Stratix GX source-synchronous circuitry with DPA. Figure 38. Source-Synchronous DPA Circuitry
Receiver Circuit rx_in+ rx_in-
Deserializer (1)
Dynamic Phase Aligner 8 Deserializer (1) rx_inclock_p rx_inclock_n xW PLL x1
Stratix GX Logic Array
Note to Figure 38:
(1) Both deserializers are identical. The deserializer operation is described in the "Principles of SERDES Operation" section.
Unlike the de-skew function in APEXTM 20KE and APEX 20KC devices, designers do not have to use a fixed training pattern with DPA in Stratix GX devices. Table 18 shows the differences between source-synchronous circuitry with DPA and source-synchronous circuitry without DPA circuitry in Stratix GX devices.
Table 18. Source-Synchronous Circuitry With & Without DPA (Part 1 of 2) Source-Synchronous Circuitry Feature Without DPA
Data rate Deserialization factors Clock frequency
With DPA
300 to 840 Megabits per 300 Mbps to 1 Gbps second (Mbps) 1, 2, 4, 8, 10 10 to 717 MHz 8, 10 74 to 717 MHz
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Table 18. Source-Synchronous Circuitry With & Without DPA (Part 2 of 2) Source-Synchronous Circuitry Feature Without DPA
Interface pins Receiver pins I/O banks 1 and 2 Dedicated inputs
With DPA
I/O banks 1 and 2 Dedicated inputs
DPA Input Support
Stratix GX device I/O banks 1 and 2 contain dedicated circuitry to support differential I/O standards at speeds up to 1 Gbps with DPA (or up to 840 Mbps without DPA). Stratix GX device source-synchronous circuitry supports LVDS, LVPECL, and 3.3-V PCML I/O standards, each with a supply voltage of 3.3 V. Refer to the High-Speed Differential I/O Interfaces in Stratix Devices chapter of the Stratix Handbook, Volume 2 for more information on these I/O standards. Transmitter pins can be either input or output pins for single-ended I/O standards. Refer to Table 19.
Table 19. Bank 1 & 2 Input Pins Input Pin Type
Differential Single ended
I/O Standard
Differential Single ended
Receiver Pin
Input only Input only
Transmitter Pin
Output only Input or output
Interface & Fast PLL
This section describes the number of channels that support DPA and their relationship with the PLL in Stratix GX devices. EP1SGX10 and EP1SGX25 devices have two dedicated fast PLLs and EP1SGX40 devices have four dedicated fast PLLs for clock multiplication. Table 20 shows the maximum number of channels in each Stratix GX device that support DPA.
Table 20. Stratix GX Source-Synchronous Differential I/O Resources (Part 1 of 2) Receiver Channels (1)
22 22 39
Device
Fast PLLs
Pin Count
Transmitter Channels (1)
22 22 39
Receiver & Transmitter Channel Speed (Gbps) (2)
1 1 1
LEs
EP1SGX10C EP1SGX10D EP1SGX25C
2 (3) 2 (3) 2
672 672 672
10,570 10,570 25,660
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Table 20. Stratix GX Source-Synchronous Differential I/O Resources (Part 2 of 2) Receiver Channels (1)
39 39 39 45 45
Device
Fast PLLs
Pin Count
Transmitter Channels (1)
39 39 39 45 45
Receiver & Transmitter Channel Speed (Gbps) (2)
1 1 1 1 1
LEs
EP1SGX25D
2
672 1,020
25,660 25,660 25,660 41,250 41,250
EP1SGX25F EP1SGX40D EP1SGX40G Notes to Table 20:
(1) (2) (3) (4)
2 4 (4) 4 (4)
1,020 1,020 1,020
This is the number of receiver or transmitter channels in the source-synchronous (I/O bank 1 and 2) interface of the device. Receiver channels operate at 1,000 Mbps with DPA. Without DPA, the receiver channels operate at 840 Mbps. One of the two fast PLLs in EP1SGX10C and EP1SGX10D devices supports DPA. Two of the four fast PLLs in EP1SGX40D and EP1SGX40G devices support DPA
The receiver and transmitter channels are interleaved so that each I/O row in I/O banks 1 and 2 of the device has one receiver channel and one transmitter channel per row. Figures 39 and 40 show the fast PLL and channels with DPA layout in EP1SGX10, EP1SGX25, and EP1SGX40 devices. In EP1SGX10 devices, only fast PLL 2 supports DPA operations.
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Figure 39. PLL & Channel Layout in EP1SGX10 & EP1SGX25 Devices Notes (1), (2)
1 Receiver 1 Transmitter
11 Rows for EP1SGX10 Devices & 19 Rows for EP1SGX25 Devices 8 1 Transmitter 1 Receiver
INCLK0
Fast PLL 1 (1)
INCLK1
Fast PLL 2
Eight-Phase Clock
1 Receiver 1 Transmitter 8 11 Rows for EP1SGX10 Devices & 20 Rows for EP1SGX25 Devices
1 Transmitter 1 Receiver
Notes to Figure 39:
(1) (2) Fast PLL 1 in EP1SGX10 devices does not support DPA. Not all eight phases are used by the receiver channel or transmitter channel in nonDPA mode.
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Figure 40. PLL & Channel Layout in EP1SGX40 Devices
CLKIN PLL (1)
Notes (1), (2)
1 Receiver 1 Transmitter
22 Rows
8 1 Transmitter 1 Receiver
INCLK0
Fast PLL 1
Eight-Phase Clock Eight-Phase Clock
INCLK1
Fast PLL 2
1 Receiver 1 Transmitter 8
23 Rows
1 Transmitter 1 Receiver
CLKIN
PLL (1)
Notes to Figure 40:
(1) (2) Corner PLLs do not support DPA. Not all eight phases are used by the receiver channel or transmitter channel in nonDPA mode.
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DPA Operation
The DPA receiver circuitry contains the dynamic phase selector, the deserializer, the synchronizer, and the data realigner (see Figure 41). This section describes the DPA operation, synchronization and data realignment. In the SERDES with DPA mode, the source clock is fed to the fast PLL through the dedicated clock input pins. This clock is multiplied by the multiplication value W to match the serial data rate. For information on the deserializer, see "Principles of SERDES Operation" on page 47. Figure 41. DPA Receiver Circuit
DPA Receiver Circuit dpll_reset Serial Data (1) Stratix GX Logic Array
rxin+ rxin-
Dynamic Phase Selector
Deserializer
10
Synchronizer 10
Data Realigner
Parallel Clock 8 inclk+ inclk xW Clock (1) x1 Clock RCLK Reset GCLK
Fast PLL
Note to Figure 41:
(1) These are phase-matched and retimed high-speed clocks and data.
The dynamic phase selector matches the phase of the high-speed clock and data before sending them to the deserializer. The fast PLL supplies eight phases of the same clock (each a separate tap from a four-stage differential VCO) to all the differential channels associated with the selected fast PLL. The DPA circuitry inside each channel locks to a phase closest to the serial data's phase and sends the retimed data and the selected clock to the deserializer. The DPA circuitry automatically performs this operation and is not selected by the designer. Each channel's DPA circuit can independently choose a different clock phase. The data phase detection and the clock phase selection process is automatic and continuous. The eight phases of the clock give the DPA circuit a granularity of one eighth of the unit interval (UI) or 125 ps at 1 Gbps. Figure 42 illustrates the clocks generated by the fast PLL circuitry and their relationship to a data stream.
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Source-Synchronous Signaling with DPA
Figure 42. Fast PLL Clocks & Data Input
Data input D0 D1 D2 D3 D4 D5 Dn
Clock A
Clock B
Clock C
Clock D
Clock A'
Clock B'
Clock C'
Clock D'
Protocols, Training Pattern & DPA Lock Time
The dynamic phase aligner uses a fast PLL for clock multiplication, and the dynamic phase selector for the phase detection and alignment. The dynamic phase aligner uses the high-speed clock out of the dynamic phase selector to deserialize high-speed data and the receiver's source synchronous operations. At each rising edge of the clock, the dynamic phase selector determines the phase difference between the clock and the data and automatically compensates for the phase difference between the data and clock.
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The actual lock time for different data patterns varies depending on the data's transition density (how often the data switches between 1 and 0) and jitter characteristic. The DPA circuitry is designed to lock onto any data pattern with sufficient transition density, so the circuitry will work with current and future protocols. Experiments and simulations show that the DPA circuitry locks when the data patterns listed in Table 21 are repeated for the specified number of times. There are other suitable patterns not shown in Table 21 and/or pattern lengths, but the lock time may vary. The circuit can adjust for any phase variation that may occur during operation.
Table 21. Training Patterns for Different Protocols Protocols
SPI-4, NPSI RapidIO Other designs SFI-4, XSBI
Training Pattern
Ten 0's, ten 1's (00000000001111111111) Four 0's, four 1's (00001111) or one 1, two 0's, one 1, four 0's (10010000) Eight alternating 1's and 0's (10101010 or
Number of Repetitions
256
01010101)
Not specified
Phase Synchronizer
Each receiver has its own phase synchronizer. The receiver phase synchronizer aligns the phase of the parallel data from all the receivers to one global clock. The synchronizers in each channel consist of a 4-bit deep and J-bit wide FIFO buffer. The parallel clock writes to the FIFO buffer and the global clock (GCLK) reads from the FIFO buffer. The global and parallel clock inputs into the synchronizers must have identical frequencies and differ only in phase. The FIFO buffer will never become full or empty (because the source and receive signals are frequency locked) when operating within the DPA specifications, and the operation does not require an empty/full flag or read/write enable signals.
Receiver Data Realignment In DPA Mode
While DPA operation aligns the incoming clock phase to the incoming data phase, it does not guarantee the parallelization boundary or byte boundary. When the dynamic phase aligner realigns the data bits, the bits may be shifted out of byte alignment, as shown in Figure 43.
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Source-Synchronous Signaling with DPA
Figure 43. Misaligned Captured Bits
Correct Alignment 0 1 2 3 4 5 6 7
Incorrect Alignment 3 4 5 6 7 0 1 2
The dynamic phase selector and synchronizer align the clock and data based on the power-up of both communicating devices, and the channel to channel skew. However, the dynamic phase selector and synchronizer cannot determine the byte boundary, and the data may need to be byte-aligned. The dynamic phase aligner's data realignment circuitry shifts data bits to correct bit misalignments. The Stratix GX circuitry contains a data-realignment feature controlled by the logic array. Stratix GX devices perform data realignment on the parallel data after the deserialization block. The data realignment can be performed per channel for more flexibility. The data alignment operation requires a state machine to recognize a specific pattern. The procedure requires the bits to be slipped on the data stream to correctly align the incoming data to the start of the byte boundary. The DPA uses its realignment circuitry and the global clock for data realignment. Either a device pin or the logic array asserts the internal rx_channel_data_align node to activate the DPA data-realignment circuitry. Switching this node from low to high activates the realignment circuitry and the data being transferred to the logic array is shifted by one bit. The data realignment block cannot be bypassed. However, if the rx_channel_data_align is not turned on (through the altvlds MegaWizard Plug-In Manager), or when it is not toggled, it will only act as a register latency. A state machine and additional logic can monitor the incoming parallel data and compare it against a known pattern. If the incoming data pattern does not match the known pattern, designers can activate the rx_channel_data_align node again. Repeat this process until the realigner detects the desired match between the known data pattern and incoming parallel data pattern.
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The DPA data-realignment circuitry allows further realignment beyond what the J multiplication factor allows. Designers can set the J multiplication factor to be 8 or 10. However, because data must be continuously clocked in on each low-speed clock cycle, the upcoming bit to be realigned and previous n - 1 bits of data are selected each time the data realignment logic's counter passes n - 1. At this point the data is selected entirely from bit-slip register 3 (see Figure 44) as the counter is reset to 0. The logic array receives a new valid byte of data on the next divided low speed clock cycle. Figure 44 shows the data realignment logic output selection from data in the data realignment register 2 and data realignment register 3 based on its current counter value upon continuous request of data slipping from the logic array. Figure 44. DPA Data Realigner
Bit Slip Bit Slip Register 2 Register 3 Bit Slip Bit Slip Register 2 Register 3 Bit Slip Bit Slip Register 2 Register 3 Bit Slip Bit Slip Register 2 Register 3 Bit Slip Bit Slip Register 2 Register 3
D19 D18 D17 D16 D15 D14 D13 D12 D11 D10
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 One bit slipped
D29 D28 D27 D26 D25 D24 D23 D22 D21 D20
D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 Seven more bits slipped
D99 D98 D97 D96 D95 D94 D93 D92 D91 D90
D89 D18 D87 D86 D85 D84 D83 D82 D81 D80 One more bit slipped
D119 D118 D117 D116 D115 D114 D113 D112 D111 D110
D99 D98 D97 D96 D95 D94 D93 D92 D91 D90 One more bit slipped
D119 D118 D117 D116 D115 D114 D113 D112 D111 D110
D109 D108 D107 D106 D125 D124 D123 D102 D101 D100
Zero bits slipped. Counter = 0 D10 is the upcoming bit to be slipped.
One bit slipped. Counter = 1 D21 is the upcoming bit to be slipped.
Eight bits slipped. Counter = 8 D98 is the upcoming bit to be slipped.
Nine bits slipped. Counter = 9 D119 is the upcoming bit to be slipped.
10 bits slipped. Counter = 0 Real data will resume on the next byte.
Use the rx_channel_data_align signal within the device to activate the data realigner. Designers can use internal logic or an external pin to control the rx_channel_data_align signal. To ensure the rising edge of the rx_channel_data_align signal is latched into the control logic, the rx_channel_data_align signal should stay high for at least two low-frequency clock cycles.
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Logic Array Blocks
To manage the alignment procedure, a state machine should be built in the FPGA logic array to generate the realignment signal. The following guidelines outline the requirements for this state machine.

The design must include an input synchronizing register to ensure that data is synchronized to the xW/J clock. After the state machine, use another synchronizing register to capture the generated rx_channel_data_align signal and synchronize it to the xW/J clock. Because the skew in the path from the output of this synchronizing register to the PLL is undefined, the state machine must generate a pulse that is high for two W/J clock periods. To guarantee the state machine does not incorrectly generate multiple rx_channel_data_align pulses to shift a single bit, the state machine must hold the rx_channel_data_align signal low for at least three x1 clock periods between pulses.
Logic Array Blocks
Each LAB consists of 10 LEs, LE carry chains, LAB control signals, local interconnect, LUT chain, and register chain connection lines. The local interconnect transfers signals between LEs in the same LAB. LUT chain connections transfer the output of one LE's LUT to the adjacent LE for fast sequential LUT connections within the same LAB. Register chain connections transfer the output of one LE's register to the adjacent LE's register within an LAB. The Quartus II Compiler places associated logic within an LAB or adjacent LABs, allowing the use of local, LUT chain, and register chain connections for performance and area efficiency. Figure 45 shows the Stratix GX LAB.
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Figure 45. Stratix GX LAB Structure
Row Interconnects of Variable Speed & Length
Direct link interconnect from adjacent block
Direct link interconnect from adjacent block
Direct link interconnect to adjacent block
Direct link interconnect to adjacent block
Local Interconnect
LAB
Three-Sided Architecture--Local Interconnect is Driven from Either Side by Columns & LABs, & from Above by Rows
Column Interconnects of Variable Speed & Length
LAB Interconnects
The LAB local interconnect can drive LEs within the same LAB. The LAB local interconnect is driven by column and row interconnects and LE outputs within the same LAB. Neighboring LABs, M512 RAM blocks, M4K RAM blocks, or DSP blocks from the left and right can also drive an LAB's local interconnect through the direct link connection. The direct link connection feature minimizes the use of row and column interconnects, providing higher performance and flexibility. Each LE can drive 30 other LEs through fast local and direct link interconnects. Figure 46 shows the direct link connection.
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Figure 46. Direct Link Connection
Direct link interconnect from left LAB, TriMatrix memory block, DSP block, or IOE output Direct link interconnect from right LAB, TriMatrix memory block, DSP block, or IOE output
Direct link interconnect to left Local Interconnect LAB
Direct link interconnect to right
LAB Control Signals
Each LAB contains dedicated logic for driving control signals to its LEs. The control signals include two clocks, two clock enables, two asynchronous clears, synchronous clear, asynchronous preset/load, synchronous load, and add/subtract control signals. This gives a maximum of 10 control signals at a time. Although synchronous load and clear signals are generally used when implementing counters, they can also be used with other functions. Each LAB can use two clocks and two clock enable signals. Each LAB's clock and clock enable signals are linked. For example, any LE in a particular LAB using the labclk1 signal will also use labclkena1. If the LAB uses both the rising and falling edges of a clock, it also uses both LAB-wide clock signals. De-asserting the clock enable signal will turn off the LAB-wide clock. Each LAB can use two asynchronous clear signals and an asynchronous load/preset signal. The asynchronous load acts as a preset when the asynchronous load data input is tied high.
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With the LAB-wide addnsub control signal, a single LE can implement a one-bit adder and subtractor. This saves LE resources and improves performance for logic functions such as DSP correlators and signed multipliers that alternate between addition and subtraction depending on data. The LAB row clocks [7..0] and LAB local interconnect generate the LABwide control signals. The MultiTrackTM interconnect's inherent low skew allows clock and control signal distribution in addition to data. Figure 47 shows the LAB control signal generation circuit. Figure 47. LAB-Wide Control Signals
Dedicated Row LAB Clocks Local Interconnect Local Interconnect 8
Local Interconnect Local Interconnect Local Interconnect Local Interconnect labclk1
labclkena1
labclkena2
syncload
labclr2
addnsub
labclk2
asyncload or labpre
labclr1
synclr
Logic Elements
The smallest unit of logic in the Stratix GX architecture, the LE, is compact and provides advanced features with efficient logic utilization. Each LE contains a four-input LUT, which is a function generator that can implement any function of four variables. In addition, each LE contains a programmable register and carry chain with carry select capability. A single LE also supports dynamic single bit addition or subtraction mode selectable by an LAB-wide control signal. Each LE drives all types of interconnects: local, row, column, LUT chain, register chain, and direct link interconnects. See Figure 48.
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Figure 48. Stratix GX LE
Register chain routing from previous LE LAB-wide Register Bypass Synchronous Load LAB-wide Packed Synchronous Register Select Clear
LAB Carry-In addnsub Carry-In1 Carry-In0
Programmable Register LUT chain routing to next LE Row, column, and direct link routing
data1 data2 data3 data4
ENA CLRN
Look-Up Table (LUT)
Carry Chain
Synchronous Load and Clear Logic
PRN/ALD D Q ADATA
Row, column, and direct link routing
labclr1 labclr2 labpre/aload Chip-Wide Reset
Asynchronous Clear/Preset/ Load Logic
Local Routing
Clock & Clock Enable Select labclk1 labclk2 labclkena1 labclkena2
Register Feedback
Register chain output
Carry-Out0 Carry-Out1 LAB Carry-Out
Each LE's programmable register can be configured for D, T, JK, or SR operation. Each register has data, true asynchronous load data, clock, clock enable, clear, and asynchronous load/preset inputs. Global signals, general-purpose I/O pins, or any internal logic can drive the register's clock and clear control signals. Either general-purpose I/O pins or internal logic can drive the clock enable, preset, asynchronous load, and asynchronous data. The asynchronous load data input comes from the data3 input of the LE. For combinatorial functions, the register is bypassed and the output of the LUT drives directly to the outputs of the LE. Each LE has three outputs that drive the local, row, and column routing resources. The LUT or register output can drive these three outputs independently. Two LE outputs drive column or row and direct link routing connections and one drives local interconnect resources. This allows the LUT to drive one output while the register drives another output. This feature, called register packing, improves device utilization because the device can use the register and the LUT for unrelated functions. Another special packing mode allows the register output to feed back into the LUT of the same LE so that the register is packed with
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its own fan-out LUT. This provides another mechanism for improved fitting. The LE can also drive out registered and unregistered versions of the LUT output.
LUT Chain & Register Chain
In addition to the three general routing outputs, the LEs within an LAB have LUT chain and register chain outputs. LUT chain connections allow LUTs within the same LAB to cascade together for wide input functions. Register chain outputs allow registers within the same LAB to cascade together. The register chain output allows an LAB to use LUTs for a single combinatorial function and the registers to be used for an unrelated shift register implementation. These resources speed up connections between LABs while saving local interconnect resources. See "MultiTrack Interconnect" on page 72 for more information on LUT chain and register chain connections.
addnsub Signal
The LE's dynamic adder/subtractor feature saves logic resources by using one set of LEs to implement both an adder and a subtractor. This feature is controlled by the LAB-wide control signal addnsub. The addnsub signal sets the LAB to perform either A + B or A - B. The LUT computes addition, and subtraction is computed by adding the two's complement of the intended subtractor. The LAB-wide signal converts to two's complement by inverting the B bits within the LAB and setting carry-in = 1 to add one to the least significant bit (LSB). The LSB of an adder/subtractor must be placed in the first LE of the LAB, where the LAB-wide addnsub signal automatically sets the carry-in to 1. The Quartus II Compiler automatically places and uses the adder/subtractor feature when using adder/subtractor parameterized functions.
LE Operating Modes
The Stratix GX LE can operate in one of the following modes:

Normal mode Dynamic arithmetic mode
Each mode uses LE resources differently. In each mode, eight available inputs to the LE--the four data inputs from the LAB local interconnect; carry-in0 and carry-in1 from the previous LE; the LAB carry-in from the previous carry-chain LAB; and the register chain connection-- are directed to different destinations to implement the desired logic function. LAB-wide signals provide clock, asynchronous clear, asynchronous preset load, synchronous clear, synchronous load, and
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Logic Elements
clock enable control for the register. These LAB-wide signals are available in all LE modes. The addnsub control signal is allowed in arithmetic mode. The Quartus II software, in conjunction with parameterized functions such as library of parameterized modules (LPM) functions, automatically chooses the appropriate mode for common functions such as counters, adders, subtractors, and arithmetic functions. If required, the designer can also create special-purpose functions that specify which LE operating mode to use for optimal performance.
Normal Mode
The normal mode is suitable for general logic applications and combinatorial functions. In normal mode, four data inputs from the LAB local interconnect are inputs to a four-input LUT (see Figure 49). The Quartus II Compiler automatically selects the carry-in or the data3 signal as one of the inputs to the LUT. Each LE can use LUT chain connections to drive its combinatorial output directly to the next LE in the LAB. Asynchronous load data for the register comes from the data3 input of the LE. LEs in normal mode support packed registers. Figure 49. LE in Normal Mode
sload sclear (LAB Wide) (LAB Wide) Register chain connection aload (LAB Wide)
addnsub (LAB Wide)
(1)
data1 data2 data3 cin (from cout of previous LE) data4
4-Input LUT
ALD/PRE ADATA Q D ENA CLRN
Row, column, and direct link routing Row, column, and direct link routing
clock (LAB Wide) ena (LAB Wide) aclr (LAB Wide)
Local routing
LUT chain connection Register chain output
Register Feedback
Note to Figure 49:
(1) This signal is only allowed in normal mode if the LE is at the end of an adder/subtractor chain.
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Dynamic Arithmetic Mode
The dynamic arithmetic mode is ideal for implementing adders, counters, accumulators, wide parity functions, and comparators. An LE in dynamic arithmetic mode uses four 2-input LUTs configurable as a dynamic adder/subtractor. The first two 2-input LUTs compute two summations based on a possible carry-in of 1 or 0; the other two LUTs generate carry outputs for the two chains of the carry select circuitry. As shown in Figure 50, the LAB carry-in signal selects either the carry-in0 or carry-in1 chain. The selected chain's logic level in turn determines which parallel sum is generated as a combinatorial or registered output. For example, when implementing an adder, the sum output is the selection of two possible calculated sums: data1 + data2 + carry-in0 or data1 + data2 + carry-in1. The other two LUTs use the data1 and data2 signals to generate two possible carry-out signals--one for a carry of 1 and the other for a carry of 0. The carry-in0 signal acts as the carry select for the carry-out0 output and carry-in1 acts as the carry select for the carry-out1 output. LEs in arithmetic mode can drive out registered and unregistered versions of the LUT output. The dynamic arithmetic mode also offers clock enable, counter enable, synchronous up/down control, synchronous clear, synchronous load, and dynamic adder/subtractor options. The LAB local interconnect data inputs generate the counter enable and synchronous up/down control signals. The synchronous clear and synchronous load options are LAB-wide signals that affect all registers in the LAB. The Quartus II software automatically places any registers that are not used by the counter into other LABs. The addnsub LAB-wide signal controls whether the LE acts as an adder or subtractor.
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Figure 50. LE in Dynamic Arithmetic Mode
LAB Carry-In Carry-In0 Carry-In1 addnsub (LAB Wide) (1) sload sclear (LAB Wide) (LAB Wide) Register chain connection aload (LAB Wide)
data1 data2 data3
LUT
ALD/PRE ADATA Q D ENA CLRN
Row, column, and direct link routing Row, column, and direct link routing
LUT
LUT
clock (LAB Wide) ena (LAB Wide) aclr (LAB Wide)
Local routing
LUT
LUT chain connection Register chain output Register Feedback
Carry-Out0 Carry-Out1
Note to Figure 50:
(1) The addnsub signal is tied to the carry input for the first LE of a carry chain only.
Carry-Select Chain
The carry-select chain provides a very fast carry-select function between LEs in arithmetic mode. The carry-select chain uses the redundant carry calculation to increase the speed of carry functions. The LE is configured to calculate outputs for a possible carry-in of 1 and carry-in of 0 in parallel. The carry-in0 and carry-in1 signals from a lower-order bit feed forward into the higher-order bit via the parallel carry chain and feed into both the LUT and the next portion of the carry chain. Carry-select chains can begin in any LE within an LAB. The speed advantage of the carry-select chain is in the parallel pre-computation of carry chains. Because the LAB carry-in selects the precomputed carry chain, not every LE is in the critical path. Only the propagation delay between LAB carry-in generation (LE 5 and LE 10) are now part of the critical path. This feature allows the Stratix GX architecture to implement high-speed counters, adders, multipliers, parity functions, and comparators of arbitrary width. Figure 51 shows the carry-select circuitry in an LAB for a 10-bit full adder. One portion of the LUT generates the sum of two bits using the input signals and the appropriate carry-in bit; the sum is routed to the output of the LE. The register can be bypassed for simple adders or used for
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accumulator functions. Another portion of the LUT generates carry-out bits. An LAB-wide carry in bit selects which chain is used for the addition of given inputs. The carry-in signal for each chain, carry-in0 or carry-in1, selects the carry-out to carry forward to the carry-in signal of the next-higher-order bit. The final carry-out signal is routed to an LE, where it is fed to local, row, or column interconnects. The Quartus II Compiler automatically creates carry chain logic during design processing, or the designer can create it manually during design entry. Parameterized functions such as LPM functions automatically take advantage of carry chains for the appropriate functions. The Quartus II Compiler creates carry chains longer than 10 LEs by linking LABs together automatically. For enhanced fitting, a long carry chain runs vertically allowing fast horizontal connections to TriMatrix memory and DSP blocks. A carry chain can continue as far as a full column.
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Logic Elements
Figure 51. Carry Select Chain
LAB Carry-In A1 B1 A2 B2
0 LE1
1 Sum1
LAB Carry-In Carry-In0 Carry-In1
LE2
Sum2
LUT data1 data2 Sum LUT
A3 B3 A4 B4
LE3
Sum3
LE4
Sum4
LUT
A5 B5
LE5
Sum5
LUT
0 A6 B6 A7 B7 A8 B8 A9 B9 A10 B10 LE6
1 Sum6
Carry-Out0
Carry-Out1
LE7
Sum7
LE8
Sum8
LE9
Sum9
LE10
Sum10
LAB Carry-Out
Clear & Preset Logic Control
LAB-wide signals control the logic for the register's clear and preset signals. The LE directly supports an asynchronous clear and preset function. The register preset is achieved through the asynchronous load of a logic high. The direct asynchronous preset does not require a NOT-gate push-back technique. Stratix GX devices support simultaneous preset/ asynchronous load, and clear signals. An asynchronous clear signal takes precedence if both signals are asserted simultaneously. Each LAB supports up to two clears and one preset signal. In addition to the clear and preset ports, Stratix GX devices provide a chip-wide reset pin (DEV_CLRn) that resets all registers in the device. An option set before compilation in the Quartus II software controls this pin. This chip-wide reset overrides all other control signals.
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MultiTrack Interconnect
In the Stratix GX architecture, connections between LEs, TriMatrix memory, DSP blocks, and device I/O pins are provided by the MultiTrack interconnect structure with DirectDriveTM technology. The MultiTrack interconnect consists of continuous, performance-optimized routing lines of different lengths and speeds used for inter- and intra-design block connectivity. The Quartus II Compiler automatically places critical design paths on faster interconnects to improve design performance. DirectDrive technology is a deterministic routing technology that ensures identical routing resource usage for any function regardless of placement within the device. The MultiTrack interconnect and DirectDrive technology simplify the integration stage of block-based designing by eliminating the re-optimization cycles that typically follow design changes and additions. The MultiTrack interconnect consists of row and column interconnects that span fixed distances. A routing structure with fixed length resources for all devices allows predictable and repeatable performance when migrating through different device densities. Dedicated row interconnects route signals to and from LABs, DSP blocks, and TriMatrix memory within the same row. These row resources include:

Direct link interconnects between LABs and adjacent blocks. R4 interconnects traversing four blocks to the right or left. R8 interconnects traversing eight blocks to the right or left. R24 row interconnects for high-speed access across the length of the device.
The direct link interconnect allows an LAB, DSP block, or TriMatrix memory block to drive into the local interconnect of its left and right neighbors and then back into itself. Only one side of a M-RAM block interfaces with direct link and row interconnects. This provides fast communication between adjacent LABs and/or blocks without using row interconnect resources. The R4 interconnects span four LABs, three LABs and one M512 RAM block, two LABs and one M4K RAM block, or two LABs and one DSP block to the right or left of a source LAB. These resources are used for fast row connections in a four-LAB region. Every LAB has its own set of R4 interconnects to drive either left or right. Figure 52 shows R4 interconnect connections from an LAB. R4 interconnects can drive and be driven by DSP blocks and RAM blocks and horizontal IOEs. For LAB interfacing, a primary LAB or LAB neighbor can drive a given R4 interconnect. For R4 interconnects that drive to the right, the primary LAB and right neighbor can drive on to the interconnect. For R4 interconnects that drive to the left, the primary LAB and its left neighbor can drive on to the interconnect. R4 interconnects can drive other R4 interconnects to extend the range of
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LABs they can drive. R4 interconnects can also drive C4 and C16 interconnects for connections from one row to another. Additionally, R4 interconnects can drive R24 interconnects. Figure 52. R4 Interconnect Connections
Adjacent LAB can Drive onto Another LAB's R4 Interconnect R4 Interconnect Driving Left C4, C8, and C16 Column Interconnects (1) R4 Interconnect Driving Right
LAB Neighbor
Primary LAB (2)
LAB Neighbor
Notes to Figure 52:
(1) (2) C4 interconnects can drive R4 interconnects. This pattern is repeated for every LAB in the LAB row.
The R8 interconnects span eight LABs, M512 or M4K RAM blocks, or DSP blocks to the right or left from a source LAB. These resources are used for fast row connections in an eight-LAB region. Every LAB has its own set of R8 interconnects to drive either left or right. R8 interconnect connections between LABs in a row are similar to the R4 connections shown in Figure 52, with the exception that they connect to eight LABs to the right or left, not four. Like R4 interconnects, R8 interconnects can drive and be driven by all types of architecture blocks. R8 interconnects can drive other R8 interconnects to extend their range as well as C8 interconnects for row-to-row connections. One R8 interconnect is faster than two R4 interconnects connected together. R24 row interconnects span 24 LABs and provide the fastest resource for long row connections between LABs, TriMatrix memory, DSP blocks, and IOEs. The R24 row interconnects can cross M-RAM blocks. R24 row interconnects drive to other row or column interconnects at every fourth LAB and do not drive directly to LAB local interconnects. R24 row interconnects drive LAB local interconnects via R4 and C4 interconnects. R24 interconnects can drive R24, R4, C16, and C4 interconnects.
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The column interconnect operates similarly to the row interconnect and vertically routes signals to and from LABs, TriMatrix memory, DSP blocks, and IOEs. Each column of LABs is served by a dedicated column interconnect, which vertically routes signals to and from LABs, TriMatrix memory and DSP blocks, and horizontal IOEs. These column resources include:

LUT chain interconnects within an LAB Register chain interconnects within an LAB C4 interconnects traversing a distance of four blocks in up and down direction C8 interconnects traversing a distance of eight blocks in up and down direction C16 column interconnects for high-speed vertical routing through the device
Stratix GX devices include an enhanced interconnect structure within LABs for routing LE output to LE input connections faster using LUT chain connections and register chain connections. The LUT chain connection allows the combinatorial output of an LE to directly drive the fast input of the LE right below it, bypassing the local interconnect. These resources can be used as a high-speed connection for wide fan-in functions from LE 1 to LE 10 in the same LAB. The register chain connection allows the register output of one LE to connect directly to the register input of the next LE in the LAB for fast shift registers. The Quartus II Compiler automatically takes advantage of these resources to improve utilization and performance. Figure 53 shows the LUT chain and register chain interconnects.
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MultiTrack Interconnect
Figure 53. LUT Chain & Register Chain Interconnects
Local Interconnect Routing Among LEs in the LAB LUT Chain Routing to Adjacent LE LE 1
Register Chain Routing to Adjacent LE's Register Input
LE 2 Local Interconnect LE 3 LE 4 LE 5 LE 6
LE 7 LE 8 LE 9
LE 10
The C4 interconnects span four LABs, M512, or M4K blocks up or down from a source LAB. Every LAB has its own set of C4 interconnects to drive either up or down. Figure 54 shows the C4 interconnect connections from an LAB in a column. The C4 interconnects can drive and be driven by all types of architecture blocks, including DSP blocks, TriMatrix memory blocks, and vertical IOEs. For LAB interconnection, a primary LAB or its LAB neighbor can drive a given C4 interconnect. C4 interconnects can drive each other to extend their range as well as drive row interconnects for column-to-column connections.
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Figure 54. C4 Interconnect Connections Note (1)
C4 Interconnect Drives Local and R4 Interconnects up to Four Rows
C4 Interconnect Driving Up
LAB
Row Interconnect
Adjacent LAB can drive onto neighboring LAB's C4 interconnect
Local Interconnect
C4 Interconnect Driving Down
Note to Figure 54:
(1) Each C4 interconnect can drive either up or down four rows.
C8 interconnects span eight LABs, M512, or M4K blocks up or down from a source LAB. Every LAB has its own set of C8 interconnects to drive either up or down. C8 interconnect connections between the LABs in a column are similar to the C4 connections shown in Figure 54 with the exception that they connect to eight LABs above and below. The C8
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interconnects can drive and be driven by all types of architecture blocks similar to C4 interconnects. C8 interconnects can drive each other to extend their range as well as R8 interconnects for column-to-column connections. C8 interconnects are faster than two C4 interconnects. C16 column interconnects span a length of 16 LABs and provide the fastest resource for long column connections between LABs, TriMatrix memory blocks, DSP blocks, and IOEs. C16 interconnects can cross MRAM blocks and also drive to row and column interconnects at every fourth LAB. C16 interconnects drive LAB local interconnects via C4 and R4 interconnects and do not drive LAB local interconnects directly. All embedded blocks communicate with the logic array similar to LABto-LAB interfaces. Each block (i.e., TriMatrix memory and DSP blocks) connects to row and column interconnects and has local interconnect regions driven by row and column interconnects. These blocks also have direct link interconnects for fast connections to and from a neighboring LAB. All blocks are fed by the row LAB clocks, labclk[7..0].
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Table 22 shows the Stratix GX device's routing scheme.
Table 22. Stratix GX Device Routing Scheme Destination Direct Link Interconnect
Local Interconnect
M512 RAM Block
R24 Interconnect
C16 Interconnect
Register Chain
M-RAM Block
Source LUT Chain
M4K RAM Block
R4 Interconnect
R8 Interconnect
C4 Interconnect
C8 Interconnect
Column IOE v
DSP Blocks
LUT Chain Register Chain Local Interconnect Direct Link Interconnect R4 Interconnect R8 Interconnect R24 Interconnect C4 Interconnect C8 Interconnect C16 Interconnect LE M512 RAM Block M4K RAM Block M-RAM Block DSP Blocks Column IOE Row IOE
v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v
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Row IOE
LE
TriMatrix Memory
TriMatrix Memory
TriMatrix memory consists of three types of RAM blocks: M512, M4K, and M-RAM blocks. Although these memory blocks are different, they can all implement various types of memory with or without parity, including true dual-port, simple dual-port, and single-port RAM, ROM, and FIFO buffers. Table 23 shows the size and features of the different RAM blocks.
Table 23. TriMatrix Memory Features (Part 1 of 2) Memory Feature
Maximum performance True dual-port memory Simple dual-port memory Single-port memory Shift register ROM FIFO buffer Byte enable Parity bits Mixed clock mode Memory initialization Simple dual-port memory mixed width support True dual-port memory mixed width support Power-up conditions Register clears Mixed-port readduring-write Outputs cleared Input and output registers Unknown output/old data
M512 RAM Block M4K RAM Block (32 x 18 Bits) (128 x 36 Bits)
(1) (1)
M-RAM Block (4K x 144 Bits)
(1)
v v v v v v v v v v v v v v v v v v v v v
Outputs cleared Input and output registers Unknown output/old data
v v v
(2)
v v v v
v v
Outputs unknown Output registers Unknown output
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Table 23. TriMatrix Memory Features (Part 2 of 2) Memory Feature
Configurations
M512 RAM Block M4K RAM Block (32 x 18 Bits) (128 x 36 Bits)
512 x1 256 x 2 128 x 4 64 x 8 64 x 9 32 x 16 32 x 18 4K x 1 2K x 2 1K x 4 512 x 8 512 x 9 256 x 16 256 x 18 128 x 32 128 x 36
M-RAM Block (4K x 144 Bits)
64K x 8 64K x 9 32K x 16 32K x 18 16K x 32 16K x 36 8K x 64 8K x 72 4K x 128 4K x 144
Notes to Table 23:
(1) (2) See Table 4-36 for maximum performance information. The M-RAM block does not support memory initializations. However, the M-RAM block can emulate a ROM function using a dual-port RAM bock. The Stratix GX device must write to the dual-port memory once and then disable the write-enable ports afterwards.
Memory Modes
TriMatrix memory blocks include input registers that synchronize writes and output registers to pipeline designs and improve system performance. M4K and M-RAM memory blocks offer a true dual-port mode to support any combination of two-port operations: two reads, two writes, or one read and one write at two different clock frequencies. Figure 55 shows true dual-port memory. Figure 55. True Dual-Port Memory Configuration
A dataA[ ] addressA[ ] wrenA clockA clockenA qA[ ] aclrA B dataB[ ] addressB[ ] wrenB clockB clockenB qB[ ] aclrB
In addition to true dual-port memory, the memory blocks support simple dual-port and single-port RAM. Simple dual-port memory supports a simultaneous read and write and can either read old data before the write occurs or just read the don't care bits. Single-port memory supports
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non-simultaneous reads and writes, but the q[] port will output the data once it has been written to the memory (if the outputs are not registered) or after the next rising edge of the clock (if the outputs are registered). For more information, see the chapter TriMatrix Embedded Memory Blocks in Stratix & Stratix GX Devices of the Stratix Device Handbook, Volume 2. Figure 56 shows these different RAM memory port configurations for TriMatrix memory. Figure 56. Simple Dual-Port & Single-Port Memory Configurations
Simple Dual-Port Memory
data[ ] wraddress[ ] wren inclock inclocken inaclr rdaddress[ ] rden q[ ] outclock outclocken outaclr
Single-Port Memory (1)
data[ ] address[ ] wren inclock inclocken inaclr
q[ ] outclock outclocken outaclr
Note to Figure 56:
(1) Two single-port memory blocks can be implemented in a single M4K block as long as each of the two independent block sizes is equal to or less than half of the M4K block size.
The memory blocks also enable mixed-width data ports for reading and writing to the RAM ports in dual-port RAM configuration. For example, the memory block can be written in x1 mode at port A and read out in x16 mode from port B. TriMatrix memory architecture can implement pipelined RAM by registering both the input and output signals to the RAM block. All TriMatrix memory block inputs are registered providing synchronous write cycles. In synchronous operation, the memory block generates its own self-timed strobe write enable (WREN) signal derived from the global or regional clock. In contrast, a circuit using asynchronous RAM must
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generate the RAM WREN signal while ensuring its data and address signals meet setup and hold time specifications relative to the WREN signal. The output registers can be bypassed. Flow-through reading is possible in the simple dual-port mode of M512 and M4K RAM blocks by clocking the read enable and read address registers on the negative clock edge and bypassing the output registers. Two single-port memory blocks can be implemented in a single M4K block as long as each of the two independent block sizes is equal to or less than half of the M4K block size. The Quartus II software automatically implements larger memory by combining multiple TriMatrix memory blocks. For example, two 256 x 16-bit RAM blocks can be combined to form a 256 x 32-bit RAM block. Memory performance does not degrade for memory blocks using the maximum number of words available in one memory block. Logical memory blocks using less than the maximum number of words use physical blocks in parallel, eliminating any external control logic that would increase delays. To create a larger high-speed memory block, the Quartus II software automatically combines memory blocks with LE control logic.
Parity Bit Support
The memory blocks support a parity bit for each byte. The parity bit, along with internal LE logic, can implement parity checking for error detection to ensure data integrity. Designers can also use parity-size data words to store user-specified control bits. In the M4K and M-RAM blocks, byte enables are also available for data input masking during write operations.
Shift Register Support
The designer can configure embedded memory blocks to implement shift registers for DSP applications such as pseudo-random number generators, multi-channel filtering, auto-correlation, and crosscorrelation functions. These and other DSP applications require local data storage, traditionally implemented with standard flip-flops, which can quickly consume many logic cells and routing resources for large shift registers. A more efficient alternative is to use embedded memory as a shift register block, which saves logic cell and routing resources and provides a more efficient implementation with the dedicated circuitry. The size of a w x m x n shift register is determined by the input data width (w), the length of the taps (m), and the number of taps (n). The size of a w x m x n shift register must be less than or equal to the maximum number of memory bits in the respective block: 576 bits for the M512
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RAM block and 4,608 bits for the M4K RAM block. The total number of shift register outputs (number of taps n x width w) must be less than the maximum data width of the RAM block (18 for M512 blocks, 36 for M4K blocks). To create larger shift registers, the memory blocks are cascaded together. Data is written into each address location at the falling edge of the clock and read from the address at the rising edge of the clock. The shift register mode logic automatically controls the positive and negative edge clocking to shift the data in one clock cycle. Figure 57 shows the TriMatrix memory block in the shift register mode. Figure 57. Shift Register Memory Configuration
w x m x n Shift Register m-Bit Shift Register w w
m-Bit Shift Register w w
n Number of Taps
m-Bit Shift Register w w
m-Bit Shift Register w w
Memory Block Size
TriMatrix memory provides three different memory sizes for efficient application support. The large number of M512 blocks are ideal for designs with many shallow first-in first-out (FIFO) buffers. M4K blocks provide additional resources for channelized functions that do not require large amounts of storage. The M-RAM blocks provide a large
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single block of RAM ideal for data packet storage. The different-sized blocks allow Stratix GX devices to efficiently support variable-sized memory in designs. The Quartus II software automatically partitions the user-defined memory into the embedded memory blocks using the most efficient size combinations. The designer can also manually assign the memory to a specific block size or a mixture of block sizes.
M512 RAM Block
The M512 RAM block is a simple dual-port memory block and is useful for implementing small FIFO buffers, DSP, and clock domain transfer applications. Each block contains 576 RAM bits (including parity bits). M512 RAM blocks can be configured in the following modes:

Simple dual-port RAM Single-port RAM FIFO ROM Shift register
When configured as RAM or ROM, the designer can use an initialization file to pre-load the memory contents. The memory address depths and output widths can be configured as 512 x 1, 256 x 2, 128 x 4, 64 x 8 (64 x 9 bits with parity), and 32 x 16 (32 x 18 bits with parity). Mixed-width configurations are also possible, allowing different read and write widths. Table 24 summarizes the possible M512 RAM block configurations.
Table 24. M512 RAM Block Configurations (Simple Dual-Port RAM) Write Port Read Port 512 x 1
512 x 1 256 x 2 128 x 4 64 x 8 32 x 16 64 x 9 32 x 18
256 x 2 v v v v v
128 x 4 v v v
64 x 8 v v v
32 x 16 v v v v
64 x 9
32 x 18
v v v v v
v
v v
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When the M512 RAM block is configured as a shift register block, a shift register of size up to 576 bits is possible. The M512 RAM block can also be configured to support serializer and deserializer applications. By using the mixed-width support in combination with DDR I/O standards, the block can function as a SERDES to support low-speed serial I/O standards using global or regional clocks. See "I/O Structure" on page 157 for details on dedicated SERDES in Stratix GX devices. M512 RAM blocks can have different clocks on its inputs and outputs. The wren, datain, and write address registers are all clocked together from one of the two clocks feeding the block. The read address, rden, and output registers can be clocked by either of the two clocks driving the block. This allows the RAM block to operate in read/write or input/output clock modes. Only the output register can be bypassed. The eight labclk signals or local interconnect can drive the inclock, outclock, wren, rden, inclr, and outclr signals. Because of the advanced interconnect between the LAB and M512 RAM blocks, LEs can also control the wren and rden signals and the RAM clock, clock enable, and asynchronous clear signals. Figure 58 shows the M512 RAM block control signal generation logic. The RAM blocks within Stratix GX devices have local interconnects to allow LEs and interconnects to drive into RAM blocks. The M512 RAM block local interconnect is driven by the R4, R8, C4, C8, and direct link interconnects from adjacent LABs. The M512 RAM blocks can communicate with LABs on either the left or right side through these row interconnects or with LAB columns on the left or right side with the column interconnects. Up to 10 direct link input connections to the M512 RAM block are possible from the left adjacent LABs and another 10 possible from the right adjacent LAB. M512 RAM outputs can also connect to left and right LABs through 10 direct link interconnects. The M512 RAM block has equal opportunity for access and performance to and from LABs on either its left or right side. Figure 59 shows the M512 RAM block to logic array interface.
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Figure 58. M512 RAM Block Control Signals
Dedicated Row LAB Clocks Local Interconnect 8
Local Interconnect
Local Interconnect Local Interconnect
Local Interconnect Local Interconnect Local Interconnect Local Interconnect inclock
inclocken
outclocken
wren
outclr
outclock
rden
inclr
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Figure 59. M512 RAM Block LAB Row Interface
C4 and C8 Interconnects R4 and R8 Interconnects 10
Direct link interconnect to adjacent LAB
Direct link interconnect to adjacent LAB dataout
Direct link interconnect from adjacent LAB
M512 RAM Block
Direct link interconnect from adjacent LAB
Control Signals datain address Clocks 2 8 Small RAM Block Local Interconnect Region LAB Row Clocks
M4K RAM Blocks
The M4K RAM block includes support for true dual-port RAM. The M4K RAM block is used to implement buffers for a wide variety of applications such as storing processor code, implementing lookup schemes, and implementing larger memory applications. Each block contains 4,608 RAM bits (including parity bits). M4K RAM blocks can be configured in the following modes:

True dual-port RAM Simple dual-port RAM Single-port RAM FIFO ROM Shift register
When configured as RAM or ROM, the designer can use an initialization file to pre-load the memory contents.
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The memory address depths and output widths can be configured as 4,096 x 1, 2,048 x 2, 1,024 x 4, 512 x 8 (or 512 x 9 bits), 256 x 16 (or 256 x 18 bits), and 128 x 32 (or 128 x 36 bits). The 128 x 32- or 36-bit configuration is not available in the true dual-port mode. Mixed-width configurations are also possible, allowing different read and write widths. Tables 25 and 26 summarize the possible M4K RAM block configurations.
Table 25. M4K RAM Block Configurations (Simple Dual-Port) Write Port Read Port 4K 1
4K x 1 2K x 2 1K x 4 512 x 8 256 x 16 128 x 32 512 x 9 256 x 18 128 x 36
2K x 2 v v v v v v
1K 4 512 8 v v v v v v v v v v v v
256 16 v v v v v v
128 32 v v v v v v
512 9
256 18
128 36
v v v v v v
v v v
v v v
v v v
Table 26. M4K RAM Block Configurations (True Dual-Port) Port B Port A 4K x 1
4K x 1 2K x 2 1K x 4 512 x 8 256 x 16 512 x 9 256 x 18
2K x 2 v v v v v
1K x 4 v v v v v
512 x 8 v v v v v
256 x 16 v v v v v
512 x 9
256 x 18
v v v v v
v v
v v
When the M4K RAM block is configured as a shift register block, the designer can create a shift register up to 4,608 bits (w x m x n).
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M4K RAM blocks support byte writes when the write port has a data width of 16, 18, 32, or 36 bits. The byte enables allow the input data to be masked so the device can write to specific bytes. The unwritten bytes retain the previous written value. Table 27 summarizes the byte selection.
Table 27. Byte Enable for M4K Blocks Notes (1), (2) byteena[3..0]
[0] = 1 [1] = 1 [2] = 1 [3] = 1 Notes to Table 27:
(1) (2) Any combination of byte enables is possible. Byte enables can be used in the same manner with 8-bit words, i.e., in x16 and x32 modes.
datain x18
[8..0] [17..9] - -
datain x36
[8..0] [17..9] [26..18] [35..27]
The M4K RAM blocks allow for different clocks on their inputs and outputs. Either of the two clocks feeding the block can clock M4K RAM block registers (renwe, address, byte enable, datain, and output registers). Only the output register can be bypassed. The eight labclk signals or local interconnects can drive the control signals for the A and B ports of the M4K RAM block. LEs can also control the clock_a, clock_b, renwe_a, renwe_b, clr_a, clr_b, clocken_a, and clocken_b signals, as shown in Figure 60. The R4, R8, C4, C8, and direct link interconnects from adjacent LABs drive the M4K RAM block local interconnect. The M4K RAM blocks can communicate with LABs on either the left or right side through these row resources or with LAB columns on either the right or left with the column resources. Up to 10 direct link input connections to the M4K RAM Block are possible from the left adjacent LABs and another 10 possible from the right adjacent LAB. M4K RAM block outputs can also connect to left and right LABs through 10 direct link interconnects each. Figure 61 shows the M4K RAM block to logic array interface.
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Figure 60. M4K RAM Block Control Signals
Dedicated Row LAB Clocks Local Interconnect 8
Local Interconnect
Local Interconnect Local Interconnect Local Interconnect clocken_a Local Interconnect clock_a renwe_a alcr_b clocken_b alcr_a renwe_b clock_b
Local Interconnect Local Interconnect Local Interconnect Local Interconnect
Figure 61. M4K RAM Block LAB Row Interface
C4 and C8 Interconnects R4 and R8 Interconnects
Direct link interconnect to adjacent LAB
10
Direct link interconnect to adjacent LAB dataout
Direct link interconnect from adjacent LAB
M4K RAM Block Byte enable Control Signals Clocks
Direct link interconnect from adjacent LAB
address
datain
8 M4K RAM Block Local Interconnect Region LAB Row Clocks
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TriMatrix Memory
M-RAM Block
The largest TriMatrix memory block, the M-RAM block, is useful for applications where a large volume of data must be stored on-chip. Each block contains 589,824 RAM bits (including parity bits). The M-RAM block can be configured in the following modes:

True dual-port RAM Simple dual-port RAM Single-port RAM FIFO RAM
The designer cannot use an initialization file to initialize the contents of a M-RAM block. All M-RAM block contents power up to an undefined value. Only synchronous operation is supported in the M-RAM block, so all inputs are registered. Output registers can be bypassed. The memory address and output width can be configured as 64K x 8 (or 64K x 9 bits), 32K x 16 (or 32K x 18 bits), 16K x 32 (or 16K x 36 bits), 8K x 64 (or 8K x 72 bits), and 4K x 128 (or 4K x 144 bits). The 4K x 128 configuration is unavailable in true dual-port mode because there are a total of 144 data output drivers in the block. Mixed-width configurations are also possible, allowing different read and write widths. Tables 28 and 29 summarizes the possible M-RAM block configurations:
Table 28. M-RAM Block Configurations (Simple Dual-Port) Write Port Read Port 64K x 9
64K x 9 32K x 18 16K x 36 8K x 72 4K x 144
32K x 18 v v v v
16K x 36 v v v v
8K x 72 v v v v
4K x 144
v v v v
v
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Table 29. M-RAM Block Configurations (True Dual-Port) Port B Port A 64K x 9
64K x 9 32K x 18 16K x 36 8K x 72
32K x 18 v v v v
16K x 36 v v v v
8K x 72 v v v v
v v v v
The read and write operation of the memory is controlled by the WREN signal, which sets the ports into either read or write modes. There is no separate read enable (RE) signal. Writing into RAM is controlled by both the WREN and byte enable (byteena) signals for each port. The default value for the byteena signal is high, in which case writing is controlled only by the WREN signal. The byte enables are available for the x18, x36, and x72 modes. In the x144 simple dual-port mode, the two sets of byteena signals (byteena_a and byteena_b) are combined to form the necessary 16 byte enables. Tables 30 and 31 summarize the byte selection.
Table 30. Byte Enable for M-RAM Blocks Notes (1), (2) byteena[3..0]
[0] = 1 [1] = 1 [2] = 1 [3] = 1 [4] = 1 [5] = 1 [6] = 1 [7] = 1
datain x18
[8..0] [17..9] - - - - - -
datain x36
[8..0] [17..9] [26..18] [35..27] - - - -
datain x72
[8..0] [17..9] [26..18] [35..27] [44..36] [53..45] [62..54] [71..63]
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TriMatrix Memory
Table 31. M-RAM Combined Byte Selection for x144 Mode Notes (1), (2) byteena[15..0]
[0] = 1 [1] = 1 [2] = 1 [3] = 1 [4] = 1 [5] = 1 [6] = 1 [7] = 1 [8] = 1 [9] = 1 [10] = 1 [11] = 1 [12] = 1 [13] = 1 [14] = 1 [15] = 1 Notes to Tables 30 and 31:
(1) (2) Any combination of byte enables is possible. Byte enables can be used in the same manner with 8-bit words, i.e., in x16, x32, x64, and x128 modes.
datain x144
[8..0] [17..9] [26..18] [35..27] [44..36] [53..45] [62..54] [71..63] [80..72] [89..81] [98..90] [107..99] [116..108] [125..117] [134..126] [143..135]
Similar to all RAM blocks, M-RAM blocks can have different clocks on their inputs and outputs. All input registers--renwe, datain, address, and byte enable registers--are clocked together from either of the two clocks feeding the block. The output register can be bypassed. The eight labclk signals or local interconnect can drive the control signals for the A and B ports of the M-RAM block. LEs can also control the clock_a, clock_b, renwe_a, renwe_b, clr_a, clr_b, clocken_a, and clocken_b signals as shown in Figure 62.
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Figure 62. M-RAM Block Control Signals
Dedicated Row LAB Clocks Local Interconnect Local Interconnect 8
Local Interconnect
Local Interconnect Local Interconnect
Local Interconnect Local Interconnect Local Interconnect
clocken_a
clocken_b
aclr_b
renwe_b
clock_a
clock_b
aclr_a
renwe_a
One of the M-RAM block's horizontal sides drive the address and control signal (clock, renwe, byteena, etc.) inputs. Typically, the horizontal side closest to the device perimeter contains the interfaces. The one exception is when two M-RAM blocks are paired next to each other. In this case, the side of the M-RAM block opposite the common side of the two blocks contains the input interface. The top and bottom sides of any M-RAM block contain data input and output interfaces to the logic array. The top side has 72 data inputs and 72 data outputs for port B, and the bottom side has another 72 data inputs and 72 data outputs for port A. Figure 63 shows an example floorplan for the EP1SGX40 device and the location of the M-RAM interfaces.
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TriMatrix Memory
Figure 63. EP1SGX40 Device with M-RAM Interface Locations Note (1)
M-RAM interface to top, bottom, and side opposite of block-to-block border. Independent M-RAM blocks interface to top, bottom, and side facing device perimeter for easy access to horizontal I/O pins.
M-RAM Block
M-RAM Block
M-RAM Block
M-RAM Block
DSP Blocks
M512 Blocks
LABs
DSP Blocks
Note to Figure 63:
(1) Device shown is an EP1SGX40 device. The number and position of M-RAM blocks varies in other devices.
The M-RAM block local interconnect is driven by the R4, R8, C4, C8, and direct link interconnects from adjacent LABs. For independent M-RAM blocks, up to 10 direct link address and control signal input connections to the M-RAM block are possible from the left adjacent LABs for M-RAM
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blocks facing to the left, and another 10 possible from the right adjacent LABs for M-RAM blocks facing to the right. For column interfacing, every M-RAM column unit connects to the right and left column lines, allowing each M-RAM column unit to communicate directly with three columns of LABs. Figures 64 through 66 show the interface between the M-RAM block and the logic array.
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TriMatrix Memory
Figure 64. Left-Facing M-RAM to Interconnect Interface Notes (1), (2)
M512 RAM Block Columns
Row Unit Interface Allows LAB Rows to Drive Address and Control Signals to M-RAM Block
LABs in Column M-RAM Boundary
Column Interface Block Drives to and from C4 and C8 Interconnects
B1 B2 B3 Port B B4 B5 B6
R11 R10 R9 R8 R7 R6 M-RAM Block
R5 R4 R3 R2
R1 A1 A2
Port A A3 A4 A5 A6
Column Interface Block Allows LAB Columns to Drive datain and dataout to and from M-RAM Block
LABs in Row M-RAM Boundary
LAB Interface Blocks
Notes to Figure 64:
(1) (2) Only R24 and C16 interconnects cross the M-RAM block boundaries. The right-facing M-RAM block has interface blocks on the right side, but none on the left. B1 to B6 and A1 to A6 orientation is clipped across the vertical axis for right-facing M-RAM blocks.
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Figure 65. M-RAM Row Unit Interface to Interconnect
C4 and C8 Interconnects R4 and R8 Interconnects M-RAM Block
LAB
10
Direct Link Interconnects addressa addressb renwe_a renwe_b byteenaA[ ] byteenaB[ ] clocken_a clocken_b clock_a clock_b aclr_a aclr_b
Up to 24
Row Interface Block M-RAM Block to LAB Row Interface Block Interconnect Region
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TriMatrix Memory
Figure 66. M-RAM Column Unit Interface to Interconnect
C4 and C8 Interconnects
LAB
LAB
LAB
M-RAM Block to LAB Row Interface Block Interconnect Region Column Interface Block
12 datain
12 dataout
M-RAM Block
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Table 32 shows the input and output data signal connections for the column units (B1 to B6 and A1 to A6). It also shows the address and control signal input connections to the row units (R1 to R11).
Table 32. M-RAM Row & Column Interface Unit Signals Unit Interface Block
R1 R2 R3 R4 R5 R6
Input SIgnals
addressa[7..0] addressa[15..8] byte_enable_a[7..0] renwe_a clock_a clocken_a clock_b clocken_b byte_enable_b[7..0] renwe_b addressb[15..8] addressb[7..0] datain_b[71..60] datain_b[59..48] datain_b[47..36] datain_b[35..24] datain_b[23..12] datain_b[11..0] datain_a[71..60] datain_a[59..48] datain_a[47..36] datain_a[35..24] datain_a[23..12] datain_a[11..0]
Output Signals
R7 R8 R9 R10 R11 B1 B2 B3 B4 B5 B6 A1 A2 A3 A4 A5 A6
dataout_b[71..60] dataout_b[59..48] dataout_b[47..36] dataout_b[35..24] dataout_b[23..12] dataout_b[11..0] dataout_a[71..60] dataout_a[59..48] dataout_a[47..36] dataout_a[35..24] dataout_a[23..12] dataout_a[11..0]
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TriMatrix Memory
Independent Clock Mode
The memory blocks implement independent clock mode for true dualport memory. In this mode, a separate clock is available for each port (ports A and B). Clock A controls all registers on the port A side, while clock B controls all registers on the port B side. Each port, A and B, also supports independent clock enables and asynchronous clear signals for port A and B registers. Figure 67 shows a TriMatrix memory block in independent clock mode.
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8 LAB Row Clocks A 8
D ENA Q
Stratix GX FPGA Family
(1)
B Data In Data In
Q D ENA
Note to Figure 67:
Memory Block 256 16 (2) 512 8 1,024 4 2,048 2 4,096 1
D ENA Q
8 dataB[ ]
dataA[ ]
byteenaA[ ] Byte Enable A
Byte Enable B
Q
D ENA
byteenaB[ ]
addressA[ ]
D ENA Q
Address A
Address B
Q
D ENA
Figure 67. Independent Clock Mode Note (1)
addressB[ ]
wrenA
wrenB
All registers shown have asynchronous clear ports.
D ENA Q
clkenA
clockA
Write Pulse Generator
Write/Read Enable
Write/Read Enable
Q
D ENA
Write Pulse Generator Data Out Data Out
clkenB clockB
D ENA
Q
Q
D ENA
Altera Corporation
qA[ ]
qB[ ]
TriMatrix Memory
Input/Output Clock Mode
Input/output clock mode can be implemented for both the true and simple dual-port memory modes. On each of the two ports, A or B, one clock controls all registers for inputs into the memory block: data input, wren, and address. The other clock controls the block's data output registers. Each memory block port, A or B, also supports independent clock enables and asynchronous clear signals for input and output registers. Figures 68 and 69 show the memory block in input/output clock mode.
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8 LAB Row Clocks 8 A
D ENA Q
Stratix GX FPGA Family
(1)
B Data In
Q D ENA
Note to Figure 68:
Data In Memory Block 256 x 16 (2) 512 x 8 1,024 x 4 2,048 x 2 4,096 x 1 Byte Enable B
D ENA Q
8 dataB[ ]
dataA[ ]
byteenaA[ ] Byte Enable A
Q
D ENA
byteenaB[ ]
addressA[ ]
D ENA Q
Address A
Address B
Q
D ENA
addressB[ ]
wrenA wrenB
D ENA Q
clkenA
Figure 68. Input/Output Clock Mode in True Dual-Port Mode Note (1)
All registers shown have asynchronous clear ports.
Write Pulse Generator Data Out Write/Read Enable Write/Read Enable
Q D ENA
clockA
Write Pulse Generator Data Out
clkenB
D ENA Q Q D ENA
clockB qA[ ] qB[ ]
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TriMatrix Memory
Figure 69. Input/Output Clock Mode in Simple Dual-Port Mode Note (1)
8 LAB Row Clocks 8 data[ ] D Q ENA Memory Block 256 16 512 8 1,024 4 2,048 2 4,096 1
Data In
address[ ]
D Q ENA
Read Address
Data Out byteena[ ] D Q ENA Byte Enable
D Q ENA
To MultiTrack Interconnect
wraddress[ ]
D Q ENA
Write Address
rden D Q ENA wren Read Enable
outclken
inclken wrclock
D Q ENA
Write Pulse Generator
Write Enable
rdclock
Note to Figure 69:
(1) All registers shown except the rden register have asynchronous clear ports.
Read/Write Clock Mode
The memory blocks implement read/write clock mode for simple dualport memory. The designer can use up to two clocks in this mode. The write clock controls the block's data inputs, wraddress, and wren. The read clock controls the data output, rdaddress, and rden. The memory blocks support independent clock enables for each clock and asynchronous clear signals for the read- and write-side registers. Figure 70 shows a memory block in read/write clock mode.
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Figure 70. Read/Write Clock Mode in Simple Dual-Port Mode Note (1)
8 LAB Row Clocks 8 data[ ] D Q ENA Memory Block 256 x 16 512 x 8 1,024 x 4 Data In 2,048 x 2 4,096 x 1 Data Out address[ ] D Q ENA Read Address D Q ENA To MultiTrack Interconnect
wraddress[ ]
D Q ENA
Write Address
byteena[ ]
D Q ENA
Byte Enable
rden D Q ENA wren Read Enable
outclken
inclken wrclock
D Q ENA
Write Pulse Generator
Write Enable
rdclock
Note to Figure 70:
(1) All registers shown except the rden register have asynchronous clear ports.
Single-Port Mode
The memory blocks also support single-port mode, used when simultaneous reads and writes are not required. See Figure 71. A single block in a memory block can support up to two single-port mode RAM blocks in the M4K RAM blocks if each RAM block is less than or equal to 2K bits in size.
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Digital Signal Processing Block
Figure 71. Single-Port Mode
8 LAB Row Clocks
8 data[ ] D Q ENA
RAM/ROM 256 x 16 512 x 8 1,024 x 4 Data In 2,048 x 2 4,096 x 1 Data Out D Q ENA
To MultiTrack Interconnect
address[ ]
D Q ENA
Address
wren
Write Enable outclken
inclken inclock
D Q ENA
Write Pulse Generator
outclock
Digital Signal Processing Block
The most commonly used DSP functions are finite impulse response (FIR) filters, complex FIR filters, infinite impulse response (IIR) filters, fast Fourier transform (FFT) functions, direct cosine transform (DCT) functions, and correlators. All of these blocks have the same fundamental building block: the multiplier. Additionally, some applications need specialized operations such as multiply-add and multiply-accumulate operations. Stratix GX devices provide DSP blocks to meet the arithmetic requirements of these functions. Each Stratix GX device has two columns of DSP blocks to efficiently implement DSP functions faster than LE-based implementations. Larger Stratix GX devices have more DSP blocks per column (see Table 33). Each DSP block can be configured to support up to:

Eight 9 x 9-bit multipliers Four 18 x 18-bit multipliers One 36 x 36-bit multiplier
As indicated, the Stratix GX DSP block can support one 36 x 36-bit multiplier in a single DSP block. This is true for any matched sign multiplications (either unsigned by unsigned or signed by signed), but
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the capabilities for dynamic and mixed sign multiplications are handled differently. The following list provides the largest functions that can fit into a single DSP block.

36 x 36-bit unsigned by unsigned multiplication 36 x 36-bit signed by signed multiplication 35 x 36-bit unsigned by signed multiplication 36 x 35-bit signed by unsigned multiplication 36 x 35-bit signed by dynamic sign multiplication 35 x 36-bit dynamic sign by signed multiplication 35 x 36-bit unsigned by dynamic sign multiplication 36 x 35-bit dynamic sign by unsigned multiplication 35 x 35-bit dynamic sign multiplication when the sign controls for each operand are different 36 x 36-bit dynamic sign multiplication when the same sign control is used for both operands This list only shows functions that can fit into a single DSP block. Multiple DSP blocks can support larger multiplication functions.
1
Figure 72 shows one of the columns with surrounding LAB rows.
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Digital Signal Processing Block
Figure 72. DSP Blocks Arranged in Columns
DSP Block Column
8 LAB Rows
DSP Block
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Table 33 shows the number of DSP blocks in each Stratix GX device.
Table 33. DSP Blocks in Stratix GX Devices Notes (1), (2) Device
EP1SGX10 EP1SGX25 EP1SGX40 Notes to Table 33:
(1) Each device has either the number of 9 x 9-, 18 x 18-, or 36 x 36-bit multipliers shown. The total number of multipliers for each device is not the sum of all the multipliers. The number of supported multiply functions shown is based on signed/signed or unsigned/unsigned implementations.
DSP Blocks
6 10 14
Total 9 x 9 Multipliers
48 80 112
Total 18 x 18 Multipliers
24 40 56
Total 36 x 36 Multipliers
6 10 14
(2)
DSP block multipliers can optionally feed an adder/subtractor or accumulator within the block depending on the configuration. This makes routing to LEs easier, saves LE routing resources, and increases performance, because all connections and blocks are within the DSP block. Additionally, the DSP block input registers can efficiently implement shift registers for FIR filter applications. Figure 73 shows the top-level diagram of the DSP block configured for 18 x 18-bit multiplier mode. Figure 74 shows the 9 x 9-bit multiplier configuration of the DSP block.
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Digital Signal Processing Block
Figure 73. DSP Block Diagram for 18 x 18-Bit Configuration
Optional Serial Shift Register Inputs from Previous DSP Block
Multiplier Stage Optional Stage Configurable as Accumulator or Dynamic Adder/Subtractor
D Q
D
Q
Output Selection Multiplexer
ENA CLRN
D
Q
ENA CLRN
ENA CLRN
Adder/ Subtractor/ Accumulator 1
D
Q
ENA CLRN
D
Q
D
Q
ENA CLRN
ENA CLRN
Summation
D
Q
ENA CLRN
D
Q
D
Q
ENA CLRN
Summation Stage for Adding Four Multipliers Together
Optional Output Register Stage
ENA CLRN
Adder/ Subtractor/ Accumulator 2
D
Q
Optional Serial Shift Register Outputs to Next DSP Block in the Column
ENA CLRN
D
Q
D
Q
ENA CLRN
Optional Pipeline Register Stage
ENA CLRN
Optional Input Register Stage with Parallel Input or Shift Register Configuration
to MultiTrack Interconnect
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Figure 74. DSP Block Diagram for 9 x 9-Bit Configuration
D Q ENA CLRN D Q ENA CLRN
D Q ENA CLRN
Adder/ Subtractor/ 1a
D Q ENA CLRN D Q ENA CLRN
D Q ENA CLRN
Summation
D Q ENA CLRN D Q ENA CLRN
D Q ENA CLRN
Adder/ Subtractor/ 1b
D Q ENA CLRN D Q ENA CLRN
D Q ENA CLRN
Output Selection Multiplexer
D Q ENA CLRN
D Q ENA CLRN D Q ENA CLRN
D Q ENA CLRN
Adder/ Subtractor/ 2a
D Q ENA CLRN D Q ENA CLRN
D Q ENA CLRN
Summation
D Q ENA CLRN D Q ENA CLRN
D Q ENA CLRN
Adder/ Subtractor/ 2b
D Q ENA CLRN D Q ENA CLRN
D Q ENA CLRN
To MultiTrack Interconnect
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Digital Signal Processing Block
The DSP block consists of the following elements:

Multiplier block Adder/output block
Multiplier Block
The DSP block multiplier block consists of the input registers, a multiplier, and pipeline register for pipelining multiply-accumulate and multiply-add/subtract functions as shown in Figure 75. Figure 75. Multiplier Sub-Block Within Stratix GX DSP Block
sign_a (1) sign_b (1) aclr[3..0] clock[3..0] ena[3..0]
shiftin B
shiftin A
Data A
D ENA
Q D ENA Q
Result to Adder blocks Optional Multiply-Accumulate and Multiply-Add Pipeline
CLRN
CLRN
Data B
D ENA
Q
CLRN
shiftout B
shiftout A
Note to Figure 75:
(1) These signals can be unregistered or registered once to match data path pipelines if required.
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Input Registers
A bank of optional input registers is located at the input of each multiplier and multiplicand inputs to the multiplier. When these registers are configured for parallel data inputs, they are driven by regular routing resources. Designers can use a clock signal, asynchronous clear signal, and a clock enable signal to independently control each set of A and B inputs for each multiplier in the DSP block. Designers select these control signals from a set of four different clock[3..0], aclr[3..0], and ena[3..0] signals that drive the entire DSP block. Designers can also configure the input registers for a shift register application. In this case, the input registers feed the multiplier and drive two dedicated shift output lines: shiftoutA and shiftoutB. The shift outputs of one multiplier block directly feed the adjacent multiplier block in the same DSP block (or the next DSP block) as shown in Figure 76, to form a shift register chain. This chain can terminate in any block, i.e., designers can create any length of shift register chain up to 224 registers. The designer can use the input shift registers for FIR filter applications. One set of shift inputs can provide data for a filter, and the other are coefficients that are optionally loaded in serial or parallel. When implementing 9 x 9- and 18 x 18-bit multipliers, the designer does not need to implement external shift registers in LAB LEs. The designer implements all the filter circuitry within the DSP block and its routing resources, saving LE and general routing resources for general logic. External registers are needed for shift register inputs when using 36 x 36-bit multipliers.
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Digital Signal Processing Block
Figure 76. Multiplier Sub-Blocks Using Input Shift Register Connections Note (1)
Data A
D ENA Q
A[n] x B[n]
CLRN D ENA Q
Data B
D ENA
Q
CLRN
CLRN
Data B
Data A
D ENA
Q
A[n 1] x B[n 1]
CLRN D ENA Q
D ENA
Q
CLRN
CLRN
Data B
Data A
D ENA
Q
A[n 2] x B[n 2]
CLRN D ENA Q
D ENA
Q
CLRN
CLRN
Note to Figure 76:
(1) Either Data A or Data B input can be set to a parallel input for constant coefficient multiplication.
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Table 34 shows the summary of input register modes for the DSP block.
Table 34. Input Register Modes Register Input Mode
Parallel input Shift register input
9x9 v v
18 x 18 v v
36 x 36 v
Multiplier
The multiplier supports 9 x 9-, 18 x 18-, or 36 x 36-bit multiplication. Each DSP block supports eight possible 9 x 9-bit or smaller multipliers. There are four multiplier blocks available for multipliers larger than 9 x 9 bits but smaller than 18 x 18 bits. There is one multiplier block available for multipliers larger than 18 x 18 bits but smaller than or equal to 36 x 36 bits. The ability to have several small multipliers is useful in applications such as video processing. Large multipliers greater than 18 x 18 bits are useful for applications such as the mantissa multiplication of a single-precision floating-point number. The multiplier operands can be signed or unsigned numbers, where the result is signed if either input is signed as shown in Table 35. The sign_a and sign_b signals provide dynamic control of each operand's representation: a logic 1 indicates the operand is a signed number, a logic 0 indicates the operand is an unsigned number. These sign signals affect all multipliers and adders within a single DSP block and designers can register them to match the data path pipeline. The multipliers are full precision (that is, 18 bits for the 18-bit multiply, 36-bits for the 36-bit multiply, and so on), regardless of whether sign_a or sign_b set the operands as signed or unsigned numbers.
Table 35. Multiplier Signed Representation Data A
Unsigned Unsigned Signed Signed
Data B
Unsigned Signed Unsigned Signed
Result
Unsigned Signed Signed Signed
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Digital Signal Processing Block
Pipeline/Post Multiply Register
The output of 9 x 9- or 18 x 18-bit multipliers can optionally feed a register to pipeline multiply-accumulate and multiply-add/subtract functions. For 36 x 36-bit multipliers, this register will pipeline the multiplier function.
Adder/Output Blocks
The result of the multiplier sub-blocks are sent to the adder/output block which consist of an adder/subtractor/accumulator unit, summation unit, output select multiplexer, and output registers. The results are used to configure the adder/output block as a pure output, accumulator, a simple two-multiplier adder, four-multiplier adder, or final stage of the 36-bit multiplier. The designer can configure the adder/output block to use output registers in any mode, and must use output registers for the accumulator. The system cannot use adder/output blocks independently of the multiplier. Figure 77 shows the adder and output stages.
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Figure 77. Adder/Output Blocks Note (1)
Accumulator Feedback accum_sload0 (2) Result A
addnsub1 (2)
Adder/ Subtractor/ Accumulator1
overflow0
Output Selection Multiplexer
Result B signa (2)
Summation signb (2)
Output Register Block
Result C
addnsub3 (2)
Adder/ Subtractor/ Accumulator2 overflow1
Result D accum_sload1 (2)
Accumulator Feedback
Notes to Figure 77:
(1) (2) Adder/output block shown in Figure 77 is in 18 x 18-bit mode. In 9 x 9-bit mode, there are four adder/subtractor blocks and two summation blocks. These signals are either not registered, registered once, or registered twice to match the data path pipeline.
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Digital Signal Processing Block
Adder/Subtractor/Accumulator
The adder/subtractor/accumulator is the first level of the adder/output block and can be used as an accumulator or as an adder/subtractor. Adder/Subtractor Each adder/subtractor/accumulator block can perform addition or subtraction using the addnsub independent control signal for each firstlevel adder in 18 x 18-bit mode. There are two addnsub[1..0] signals available in a DSP block for any configuration. For 9 x 9-bit mode, one addnsub[1..0] signal controls the top two one-level adders and another addnsub[1..0] signal controls the bottom two one-level adders. A high addnsub signal indicates addition, and a low signal indicates subtraction. The addnsub control signal can be unregistered or registered once or twice when feeding the adder blocks to match data path pipelines. The signa and signb signals serve the same function as the multiplier block signa and signb signals. The only difference is that these signals can be registered up to two times. These signals are tied to the same signa and signb signals from the multiplier and must be connected to the same clocks and control signals. Accumulator When configured for accumulation, the adder/output block output feeds back to the accumulator as shown in Figure 77. The accum_sload[1..0] signal synchronously loads the multiplier result to the accumulator output. This signal can be unregistered or registered once or twice. Additionally, the overflow signal indicates the accumulator has overflowed or underflowed in accumulation mode. This signal is always registered and must be externally latched in LEs if the design requires a latched overflow signal.
Summation
The output of the adder/subtractor/accumulator block feeds to an optional summation block. This block sums the outputs of the DSP block multipliers. In 9 x 9-bit mode, there are two summation blocks providing the sums of two sets of four 9 x 9-bit multipliers. In 18 x 18-bit mode, there is one summation providing the sum of one set of four 18 x 18-bit multipliers.
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Output Selection Multiplexer
The outputs from the various elements of the adder/output block are routed through an output selection multiplexer. Based on the DSP block operational mode and user settings, the multiplexer selects whether the output from the multiplier, the adder/subtractor/accumulator, or summation block feeds to the output.
Output Registers
Optional output registers for the DSP block outputs are controlled by four sets of control signals: clock[3..0], aclr[3..0], and ena[3..0]. Output registers can be used in any mode.
Modes of Operation
The adder, subtractor, and accumulate functions of a DSP block have four modes of operation:

Simple multiplier Multiply-accumulator Two-multipliers adder Four-multipliers adder Each DSP block can only support one mode. Mixed modes in the same DSP block is not supported.
1
Simple Multiplier Mode
In simple multiplier mode, the DSP block drives the multiplier sub-block result directly to the output with or without an output register. Up to four 18 x 18-bit multipliers or eight 9 x 9-bit multipliers can drive their results directly out of one DSP block. See Figure 78.
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Digital Signal Processing Block
Figure 78. Simple Multiplier Mode
signa (1) signb (1) aclr clock ena
shiftin B
shiftin A
Data A
D ENA
Q D ENA Q D ENA Q
Data Out
CLRN
CLRN CLRN
Data B
D ENA
Q
CLRN
shiftout B
shiftout A
Note to Figure 78:
(1) These signals are not registered or registered once to match the data path pipeline.
DSP blocks can also implement one 36 x 36-bit multiplier in multiplier mode. DSP blocks use four 18 x 18-bit multipliers combined with dedicated adder and internal shift circuitry to achieve 36-bit multiplication. The input shift register feature is not available for the 36 x 36-bit multiplier. In 36 x 36-bit mode, the device can use the register that is normally a multiplier-result-output register as a pipeline stage for the 36 x 36-bit multiplier. Figure 79 shows the 36 x 36-bit multiply mode.
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Figure 79. 36 x 36 Multiply Mode
signa (1) signb (1) aclr clock ena
A[17..0]
D ENA
Q D ENA Q
CLRN
CLRN
B[17..0]
D ENA
Q
CLRN
A[35..18]
D ENA
Q D ENA Q D ENA Q
Data Out
CLRN
CLRN
36 x 36 Multiplier Adder signa (2) signb (2)
CLRN
B[35..18]
D ENA
Q
CLRN
A[35..18]
D ENA
Q D ENA Q
CLRN
CLRN
B[17..0]
D ENA
Q
CLRN
A[17..0]
D ENA
Q D ENA Q
CLRN
CLRN
B[35..18]
D ENA
Q
CLRN
Notes to Figure 79:
(1) (2) These signals are not registered or registered once to match the pipeline. These signals are not registered, registered once, or registered twice for latency to match the pipeline.
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Digital Signal Processing Block
Multiply-Accumulator Mode
In multiply-accumulator mode (see Figure 80), the DSP block drives multiplied results to the adder/subtractor/accumulator block configured as an accumulator. A designer can implement one or two multiplyaccumulators up to 18 x 18 bits in one DSP block. The first and third multiplier sub-blocks are unused in this mode, since only one multiplier can feed one of two accumulators. The multiply-accumulator output can be up to 52 bits--a maximum of a 36-bit result with 16 bits of accumulation. The accum_sload and overflow signals are only available in this mode. The addnsub signal can set the accumulator for decimation and the overflow signal will indicate underflow condition. Figure 80. Multiply-Accumulate Mode
signa (1) signb (1) aclr clock ena Shiftin B Shiftin A
Data A
D ENA
Q D ENA Q D ENA Q
Data Out
Accumulator
CLRN
CLRN CLRN
Data B
D ENA
Q
overflow
CLRN
Shiftout B
Shiftout A
addnsub (2) signa (2) signb (2) accum_sload (2)
Notes to Figure 80:
(1) (2) These signals are not registered or registered once to match the data path pipeline. These signals are not registered, registered once, or registered twice for latency to match the data path pipeline.
Two-Multipliers Adder Mode
The two-multipliers adder mode uses the adder/subtractor/accumulator block to add or subtract the outputs of the multiplier block, which is useful for applications such as FFT functions and complex FIR filters. A single DSP block can implement two sums or differences from two 18 x 18-bit multipliers each or four sums or differences from two 9 x 9-bit multipliers each.
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Designers can use the two-multipliers adder mode for complex multiplications, which are written as: (a + jb) x (c + jd) = [(a x c) - (b x d)] + j x [(a x d) + (b x c)] The two-multipliers adder mode allows a single DSP block to calculate the real part [(a x c) - (b x d)] using one subtractor and the imaginary part [(a x d) + (b x c)] using one adder, for data widths up to 18 bits. Two complex multiplications are possible for data widths up to 9 bits using four adder/subtractor/accumulator blocks. Figure 81 shows an 18-bit two-multipliers adder. Figure 81. Two-Multipliers Adder Mode Implementing Complex Multiply
18 A 36 18 C 18 B 36 18 D 18 A 36 18 D 18 B 36 18 C Adder 37 (A x D) + (B x C) (Imaginary Part) 18 18 Subtractor 18 37 (A x C) - (B x D) (Real Part) 18 DSP Block
Four-Multipliers Adder Mode
In the four-multipliers adder mode, the DSP block adds the results of two first -stage adder/subtractor blocks. One sum of four 18 x 18-bit multipliers or two different sums of two sets of four 9 x 9-bit multipliers can be implemented in a single DSP block. The product width for each multiplier must be the same size. The four-multipliers adder mode is useful for FIR filter applications. Figure 82 shows the four multipliers adder mode.
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Digital Signal Processing Block
Figure 82. Four-Multipliers Adder Mode
signa (1) signb (1) aclr clock ena shiftin B shiftin A
Data A
D ENA
Q D ENA Q
CLRN
Adder/Subtractor
CLRN
Data B
D ENA
Q
CLRN
Data A
D ENA
Q D ENA Q D ENA Q
Data Out
CLRN
CLRN
addnsub1 (2) signa (2) signb (2) addnsub3 (2)
Summation
CLRN
Data B
D ENA
Q
CLRN
Data A
D ENA
Q D ENA Q
CLRN
Adder/Subtractor
CLRN
Data B
D ENA
Q
CLRN
Data A
D ENA
Q D ENA Q
CLRN
CLRN
Data B
D ENA
Q
CLRN
shiftout B
shiftout A
Notes to Figure 82:
(1) (2) These signals are not registered or registered once to match the data path pipeline. These signals are not registered, registered once, or registered twice for latency to match the data path pipeline.
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For FIR filters, the DSP block combines the four-multipliers adder mode with the shift register inputs. One set of shift inputs contains the filter data, while the other holds the coefficients loaded in serial or parallel. The input shift register eliminates the need for shift registers external to the DSP block (i.e., implemented in LEs). This architecture simplifies filter design since the DSP block implements all of the filter circuitry. One DSP block can implement an entire 18-bit FIR filter with up to four taps. For FIR filters larger than four taps, DSP blocks can be cascaded with additional adder stages implemented in LEs. Table 36 shows the different number of multipliers possible in each DSP block mode according to size. These modes allow the DSP blocks to implement numerous applications for DSP including FFTs, complex FIR, FIR, and 2D FIR filters, equalizers, IIR, correlators, matrix multiplication and many other functions.
Table 36. Multiplier Size & Configurations per DSP block DSP Block Mode
Multiplier Multiply-accumulator Two-multipliers adder Four-multipliers adder Note to Table 36:
(1) The number of supported multiply functions shown is based on signed/signed or unsigned/unsigned implementations.
9x9
Eight multipliers with eight product outputs Two multiply and accumulate (52 bits) Four sums of two multiplier products each Two sums of four multiplier products each
18 x 18
Four multipliers with four product outputs Two multiply and accumulate (52 bits) Two sums of two multiplier products each One sum of four multiplier products each
36 x 36 (1)
One multiplier with one product output - - -
DSP Block Interface
Stratix GX device DSP block outputs can cascade down within the same DSP block column. Dedicated connections between DSP blocks provide fast connections between the shift register inputs to cascade the shift register chains. The designer can cascade DSP blocks for 9 x 9- or 18 x 18bit FIR filters larger than four taps, with additional adder stages implemented in LEs. If the DSP block is configured as 36 x 36 bits, the adder, subtractor, or accumulator stages are implemented in LEs. Each DSP block can route the shift register chain out of the block to cascade two full columns of DSP blocks.
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Digital Signal Processing Block
The DSP block is divided into eight block units that interface with eight LAB rows on the left and right. Each block unit can be considered half of an 18 x 18-bit multiplier sub-block with 18 inputs and 18 outputs. A local interconnect region is associated with each DSP block. Like an LAB, this interconnect region can be fed with 10 direct link interconnects from the LAB to the left or right of the DSP block in the same row. All row and column routing resources can access the DSP block's local interconnect region. The outputs also work similarly to LAB outputs as well. Nine outputs from the DSP block can drive to the left LAB through direct link interconnects and nine can drive to the right LAB though direct link interconnects. All 18 outputs can drive to all types of row and column routing. Outputs can drive right- or left-column routing. Figures 83 and 84 show the DSP block interfaces to LAB rows. Figure 83. DSP Block Interconnect Interface
DSP Block OA[17..0]
MultiTrack Interconnect
MultiTrack Interconnect
A1[17..0] OB[17..0]
B1[17..0] OC[17..0]
A2[17..0] OD[17..0]
B2[17..0] OE[17..0]
A3[17..0] OF[17..0]
B3[17..0] OG[17..0]
A4[17..0] OH[17..0]
B4[17..0]
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Figure 84. DSP Block Interface to Interconnect
C4 and C8 Interconnects Direct Link Interconnect from Adjacent LAB R4 and R8 Interconnects Nine Direct Link Outputs to Adjacent LABs Direct Link Interconnect from Adjacent LAB
18 DSP Block Row Structure 10 9 9
LAB
LAB
10
3 Control 18 [17..0] [17..0] 18
Row Interface Block DSP Block to LAB Row Interface Block Interconnect Region 18 Inputs per Row 18 Outputs per Row
A bus of 18 control signals feeds the entire DSP block. These signals include clock[0..3] clocks, aclr[0..3] asynchronous clears, ena[1..4] clock enables, signa, signb signed/unsigned control signals, addnsub1 and addnsub3 addition and subtraction control signals, and accum_sload[0..1] accumulator synchronous loads. The
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clock signals are routed from LAB row clocks and are generated from specific LAB rows at the DSP block interface. The LAB row source for control signals, data inputs, and outputs is shown in Table 37.
Table 37. DSP Block Signal Sources & Destinations LAB Row at Interface
1 2 3
Control Signals Generated
signa aclr0 accum_sload0 addnsub1 clock0 ena0 aclr1 clock1 ena1 aclr2 clock2 ena2 sign_b clock3 ena3 clear3 accum_sload1 addnsub3
Data Inputs
A1[17..0] B1[17..0] A2[17..0]
Data Outputs
OA[17..0] OB[17..0] OC[17..0]
4
B2[17..0]
OD[17..0]
5
A3[17..0]
OE[17..0]
6
B3[17..0]
OF[17..0]
7 8
A4[17..0] B4[17..0]
OG[17..0] OH[17..0]
PLLs & Clock Networks
Stratix GX devices provide a hierarchical clock structure and multiple PLLs with advanced features. The large number of clocking resources in combination with the clock synthesis precision provided by enhanced and fast PLLs provides a complete clock management solution. Stratix GX devices contain up to four enhanced PLLs and up to four fast PLLs. In addition, there are four receiver PLLs and one transmitter PLL per transceiver block located on the right side of Stratix GX devices.
Global & Hierarchical Clocking
Stratix GX devices provide 16 dedicated global clock networks, 16 regional clock networks (four per device quadrant), 8 dedicated fast regional clock networks within EP1SGX10 and EP1SGX25, and 16 dedicated fast regional clock networks within EP1SGX40 devices.
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These clocks are organized into a hierarchical clock structure that allows for up to 22 clocks per device region with low skew and delay. This hierarchical clocking scheme provides up to 40 unique clock domains within EP1SGX10 and EP1SGX25 devices, and 48 unique clock domains within EP1SGX40 devices. There are 12 dedicated clock pins (CLK[15..12], and CLK[7..0]) to drive either the global or regional clock networks. Three clock pins drive the top, bottom, and left side of the device. Enhanced and fast PLL outputs as well as an I/O interface can also drive these global and regional clock networks. There are up to 20 recovered clocks (rxclkout[20..0]) and up to 5 transmitter clock outputs (coreclk_out) which can drive any of the global clock networks (CLK[15..0]), as shown in Figure 85.
Global Clock Network
These clocks drive throughout the entire device, feeding all device quadrants. The global clock networks can be used as clock sources for all resources within the device IOEs, LEs, DSP blocks, and all memory blocks. These resources can also be used for control signals, such as clock enables and synchronous or asynchronous clears fed from the external pin. The global clock networks can also be driven by internal logic for internally generated global clocks and asynchronous clears, clock enables, or other control signals with large fanout. Figure 85 shows the 12 dedicated CLK pins and the transceiver clocks driving global clock networks.
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PLLs & Clock Networks
Figure 85. Global Clock Resources
CLK[15..12]
CLK[3..0]
Global Clock [15..0]
Transceiver Clocks
CLK[7..4]
Regional Clock Network
There are four regional clock networks RCLK[3..0] within each quadrant of the Stratix GX device that are driven by the same dedicated CLK[7..0] and CLK[15..12] input pins, PLL outputs, or transceiver clocks. The regional clock networks only pertain to the quadrant they drive into. The regional clock networks provide the lowest clock delay and skew for logic contained within a single quadrant. The CLK clock pins symmetrically drive the RCLK networks within a particular quadrant, as shown in Figure 86.
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Figure 86. Regional Clocks
RCLK[15..14] RCLK[13..12]
CLK[15..12]
RCLK[1..0] CLK[3..0]
RCLK[11..10] Transceiver Clocks RCLK[9..8]
RCLK[3..2]
CLK[7..4] Regional Clocks Only Drive a Device Quadrant from Specified CLK Pins, Recovered Clocks, or PLLs within that Quadrant
RCLK[5..4]
RCLK[7..6]
Fast Regional Clock Network
In EP1SGX25 and EP1SGX10 devices, there are two fast regional clock networks, FCLK[1..0], within each quadrant, fed by input pins (see Figure 87). In EP1SGX40 devices, there are two fast regional clock networks within each half-quadrant (see Figure 88). The FCLK[1..0] clocks can also be used for high fanout control signals, such as asynchronous clears, presets, clock enables, or protocol control signals such as TRDY and IRDY for PCI. Dual-purpose FCLK pins drive the fast clock networks. All devices have eight FCLK pins to drive fast regional clock networks. Any I/O pin can drive a clock or control signal onto any fast regional clock network with the addition of a delay. The I/O interconnect drives this signal.
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Figure 87. EP1SGX25 & EP1SGX10 Device Fast Clock Pin Connections to Fast Regional Clocks
Fast Clock [3..2] Fast Clock [1..0]
FCLK[1..0]
FCLK[1..0]
FCLK[1..0]
FCLK[1..0]
[5..4]
[7..6]
Fast Clock
Fast Clock
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Figure 88. EP1SGX40 Device Fast Regional Clock Pin Connections to Fast Regional Clocks
Fast Clock [3] Fast Clock [2] Fast Clock [1] Fast Clock [0]
fclk[1..0]
[4]
[5]
[6]
[7]
Fast Clock
Fast Clock
Fast Clock
Fast Clock
Combined Resources
Within each region, there are 22 distinct dedicated clocking resources consisting of 16 global clock lines, 4 regional clock lines, and 2 fast regional clock lines. Multiplexers are used with these clocks to form 8-bit busses to drive LAB row clocks, column IOE clocks, or row IOE clocks. Another multiplexer is used at the LAB level to select two of the eight row clocks to feed the LE registers within the LAB. See Figure 89.
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PLLs & Clock Networks
Figure 89. Regional Clock Bus
Clocks Available to a Quadrant or Half-Quadrant Global Clock Network [15..0] Regional Clock Network [3..0] Fast Regional Clock Network [1..0] Horizontal I/O Cell IO_CLK[7..0] Clock [21:0] Lab Row Clock [7..0] Vertical I/O Cell IO_CLK[7..0]
IOE clocks have horizontal and vertical block regions that are clocked by eight I/O clock signals chosen from the 22-quadrant or half-quadrant clock resources. Figures 90 and 91 show the quadrant and half-quadrant relationship to the I/O clock regions, respectively. The vertical regions (column pins) have less clock delay than the horizontal regions (row pins).
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Figure 90. EP1SGX25 & EP1SGX10 Device I/O Clock Groups
IO_CLKA[7:0] IO_CLKB[7:0]
8
8 I/O Clock Regions
8 13 22 Clocks in the Quadrant IO_CLKH[7:0] 14 22 Clocks in the Quadrant
8 IO_CLKG[7:0] 22 Clocks in the Quadrant
16
22 Clocks in the Quadrant 15
8
8
IO_CLKF[7:0]
IO_CLKE[7:0]
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PLLs & Clock Networks
Figure 91. EP1SGX40 Device I/O Clock Groups
IO_CLKA[7:0] IO_CLKB[7:0] IO_CLKC[7:0] IO_CLKD[7:0]
8
8
8
8 I/O Clock Regions
8 13 IO_CLKP[7:0] 22 Clocks in the Half-Quadrant 8 14 IO_CLKO[7:0] 22 Clocks in the Half-Quadrant 22 Clocks in the Half-Quadrant 22 Clocks in the Half-Quadrant
8 17 IO_CLKN[7:0]
8
22 Clocks in the Half-Quadrant
22 Clocks in the Half-Quadrant
22 Clocks in the Half-Quadrant
22 Clocks in the Half-Quadrant
16
IO_CLKM[7:0]
15
8
8
8
8
IO_CLKL[7:0]
IO_CLKK[7:0]
IO_CLKJ[7:0]
IO_CLKI[7:0]
Designers can use the Quartus II software to control whether a clock input pin is either global, regional, or fast regional. The Quartus II software automatically selects the clocking resources if not specified.
Enhanced & Fast PLLs
Stratix GX devices provide robust clock management and synthesis using up to four enhanced PLLs and four fast PLLs. These PLLs increase performance and provide advanced clock interfacing and clock frequency synthesis. With features such as clock switchover, spread spectrum
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clocking, programmable bandwidth, phase and delay control, and dynamic PLL reconfiguration, the Stratix GX device's enhanced PLLs provide designers with complete control of their clocks and system timing. The fast PLLs provide general purpose clocking with multiplication and phase shifting as well as high-speed outputs for highspeed differential I/O support. Enhanced and fast PLLs work together with the Stratix GX high-speed I/O and advanced clock architecture to provide significant improvements in system performance and bandwidth. The Quartus II software enables the PLLs and their features without requiring any external devices. Table 38 shows which PLLs are available for each Stratix GX device and their type. Table 39 shows the enhanced PLL and fast PLL features in Stratix GX devices.
Table 38. Stratix GX Device PLL Availability Fast PLLs Device 1
EP1SGX10 EP1SGX25 EP1SGX40 v v v
Enhanced PLLs 8 9 (1) 10 (1) 5 (2)
v v
2
v v v
3 (1)
4 (1)
7
6 (2)
v v v
11 (3) 12 (3)
v
v
v
v
v
Notes to Table 38:
(1) (2) (3) PLLs 3, 4, 9, and 10 are not available in Stratix GX devices. However, these PLLs are listed in Table 38 because the Stratix GX PLL numbering scheme is consistent with Stratix devices. PLLs 5 and 6 each have eight single-ended outputs or four differential outputs. PLLs 11 and 12 each have one single-ended output.
Table 39. Stratix GX Enhanced PLL & Fast PLL Features (Part 1 of 2) Feature
Clock multiplication and division Phase shift Delay shift Clock switchover PLL reconfiguration Programmable bandwidth Spread spectrum clocking Programmable duty cycle Number of internal clock outputs
Notes (1)-(8) Fast PLL
m/(post-scale counter) (2) Down to 125-ps increments (3), (4)
Enhanced PLL
m/ (n x post-scale counter) (1) Down to 156.25-ps increments (3), (4) 250-ps increments for 3 ns v v v v v 6
v 3 (5)
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Table 39. Stratix GX Enhanced PLL & Fast PLL Features (Part 2 of 2) Feature
Number of external clock outputs Number of feedback clock inputs Notes to Table 39:
(1) (2) (3) (4) (5) (6) (7) (8)
Notes (1)-(8) Fast PLL
(7)
Enhanced PLL
Four differential/eight singled-ended or one single-ended (6) 4 (8)
The maximum count value is 1024, with a 50% duty cycle setting on the counter. The maximum count value for any other duty cycle setting is 512. For fast PLLs, m and post-scale counters range from 1 to 32. The smallest phase shift is determined by the VCO period divided by 8. For degree increments, Stratix GX devices can shift all output frequencies in increments of at least 45. Smaller degree increments are possible depending on the frequency and divide parameters. PLLs 7 and 8 have two output ports per PLL. PLLs 1 and 2 have three output ports per PLL. Every Stratix GX device has two enhanced PLLs (PLLs 5 and 6) with eight single-ended or four differential outputs each. Two additional enhanced PLLs (PLLs 11 and 12) in EP1SGX40 devices each have one single-ended output. Fast PLLs can drive to any I/O pin as an external clock. For high-speed differential I/O pins, the device uses a data channel to generate txclkout. Every Stratix GX device has two enhanced PLLs with one single-ended or differential external feedback input per PLL.
Figure 92 shows a top-level diagram of the Stratix GX device and the PLL floorplan.
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Figure 92. PLL Floorplan
CLK[15..12] 5 11 High-Speed Transceivers inclk1
FPLL7CLK
7
inclk2
CLK[3..0]
1 2
inclk3
inclk4 PLLs
inclk5 FPLL8CLK 8
6
12
CLK[7..4]
Figure 93 shows the global and regional clock connections from the PLL outputs and the CLK pins.
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PLLs & Clock Networks
Figure 93. Global & Regional Clock Connections From Side Pins & Fast PLL Outputs
RCLK1 RCLK0
FPLL7CLK
Note (1)
G3
G1 G0 G2
l0
PLL 7 l1
g0
CLK0 CLK1
l0
PLL 1 l1
g0
CLK2 CLK3
l0 2 PLL 2 l1 g0
l0
PLL 8 l1 g0
FPLL8CLK
RCLK2 RCLK3
Global Clocks
Regional Clocks
Note to Figure 93:
(1) PLLs 1,2 7, and 8 are fast PLLs. PLLs 7 and 8 do not drive global clocks.
Figure 94 shows the global and regional clocking from enhanced PLL outputs and top CLK pins.
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Figure 94. Global & Regional Clock Connections From Top Clock Pins & Enhanced PLL Outputs
PLL5_OUT[3..0] CLK14 PLL5_FB CLK15 CLK12 CLK13
Note (1)
E[0..3] PLL 5 PLL 11
L0 L1 G0 G1 G2 G3
G0 G1 G2 G3 L0 L1
PLL11_OUT RCLK12 RCLK13
Regional Clocks
RCLK14 RCLK15 G12 G13 G14 G15
Global Clocks
G4 G5 G6 G7
Regional Clocks
RCLK4 RCLK5 RCLK6 RCLK7
PLL12_OUT
L0 L1 G0 G1 G2 G3 PLL 6
G0 G1 G2 G3 L0 L1 PLL 12
PLL6_OUT[3..0]
PLL6_FB CLK4
CLK5
CLK6
CLK7
Note to Figure 94:
(1) PLLs 5, 6, 11, and 12 are enhanced PLLs.
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PLLs & Clock Networks
Enhanced PLLs
Stratix GX devices contain up to four enhanced PLLs with advanced clock management features. Figure 95 shows a diagram of the enhanced PLL. Figure 95. Stratix GX Enhanced PLL
Post-Scale Counters VCO Phase Selection Selectable at Each PLL Output Port From Adjacent PLL t Regional Clocks Clock Switch-Over Circuitry CLK0 /n t PFD Charge Pump Loop Filter 8 VCO /g0 /l1 Phase Frequency Detector Spread Spectrum 4 t Programmable Time Delay on Each PLL Port
/l0
t
Global Clocks
CLK1
/g1
t t t I/O Buffers (2) to I/O or general routing
(1)
t
/m
/g2
/g3 FBIN Lock Detect & Filter VCO Phase Selection Affecting All Outputs /e0
t t t t I/O Buffers (3)
/e1
4
/e2 /e3
Notes to Figure 95:
(1) (2) (3) External feedback is available in PLLs 5 and 6. This external output is available from the g0 counter for PLLs 11 and 12. These counters and external outputs are available in PLLs 5 and 6.
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Clock Multiplication & Division
Each Stratix GX device enhanced PLL provides clock synthesis for PLL output ports using m/(n x post-scale counter) scaling factors. The input clock is divided by a pre-scale divider, n, and is then multiplied by the m feedback factor. The control loop drives the VCO to match fIN x (m/n). Each output port has a unique post-scale counter that divides down the high-frequency VCO. For multiple PLL outputs with different frequencies, the VCO is set to the least common multiple of the output frequencies that meets its frequency specifications. Then, the post-scale dividers scale down the output frequency for each output port. For example, if output frequencies required from one PLL are 33 and 66 MHz, set the VCO to 330 MHz (the least common multiple in the VCO's range). There is one pre-scale divider, n, and one multiply divider, m, per PLL, with a range of 1 to 512 on each. There are two post-scale dividers (l) for regional clock output ports, four counters (g) for global clock output ports, and up to four counters (e) for external clock outputs, all ranging from 1 to 512. The Quartus II software automatically chooses the appropriate scaling factors according to the input frequency, multiplication, and division values entered.
Clock Switchover
To effectively develop high-reliability network systems, clocking schemes must support multiple clocks to provide redundancy. For this reason, Stratix GX device enhanced PLLs support a flexible clock switchover capability. Figure 96 shows a block diagram of the switchover circuit.The switchover circuit is configurable, so designers can define how to implement it. Clock-sense circuitry automatically switches from the primary to secondary clock for PLL reference when the primary clock signal is not present.
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PLLs & Clock Networks
Figure 96. Clock Switchover Circuitry
CLK0_BAD CLK1_BAD Active Clock SMCLKSW
Clock Sense
Switch-Over State Machine
CLKLOSS
CLKSWITCH
t CLK0 CLK1 MUXOUT
n Counter
PFD
FBCLK
Enhanced PLL
Note to Figure 96:
(1) PFD: phase frequency detector.
There are two possible ways to use the clock switchover feature.
Designers can use automatic switchover circuitry for switching between inputs of the same frequency. For example, in applications that require a redundant clock with the same frequency as the primary clock, the switchover state machine generates a signal that controls the multiplexer select input on the bottom of Figure 96. In this case, the secondary clock becomes the reference clock for the PLL. Designers can use the clkswitch input for user- or systemcontrolled switch conditions. This is possible for same-frequency switchover or to switch between inputs of different frequencies. For example, if inclk0 is 66 MHz and inclk1 is 100 MHz, designers must control the switchover because the automatic clock-sense circuitry cannot monitor primary and secondary clock frequencies with a frequency difference of more than 20%. This feature is useful
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when clock sources can originate from multiple cards on the backplane, requiring a system-controlled switchover between frequencies of operation. Designers can use clkswitch together with the lock signal to trigger the switch from a clock that is running but becomes unstable and cannot be locked onto. During switchover, the PLL VCO continues to run and will either slow down or speed up, generating frequency drift on the PLL outputs. The clock switchover transitions without any glitches. After the switch, there is a finite resynchronization period to lock onto new clock as the VCO ramps up. The exact amount of time it takes for the PLL to relock relates to the PLL configuration and may be adjusted by using the programmable bandwidth feature of the PLL. The preliminary specification for the maximum time to relock is 100 s.
f
For more information on clock switchover, see AN313: Implementing Clock Switchover in Stratix & Stratix GX Devices.
PLL Reconfiguration
The PLL reconfiguration feature enables system logic to change Stratix GX device enhanced PLL counters and delay elements without reloading a Programmer Object File (.pof). This provides considerable flexibility for frequency synthesis, allowing real-time PLL frequency and output clock delay variation. The designer can sweep the PLL output frequencies and clock delay in prototype environments. The PLL reconfiguration feature can also dynamically or intelligently control system clock speeds or tCO delays in end systems. Clock delay elements at each PLL output port implement variable delay. Figure 97 shows a diagram of the overall dynamic PLL control feature for the counters and the clock delay elements. The configuration time is less than 20 s for the enhanced PLL using a input shift clock rate of 25 MHz. The charge pump, loop filter components, and phase shifting using VCO phase taps cannot be dynamically adjusted.
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PLLs & Clock Networks
Figure 97. Dynamically Programmable Counters & Delays in Stratix GX Device Enhanced PLLs
Counters and Clock Delay Settings are Programmable All Output Counters and Clock Delay Settings can be Programmed Dynamically
fREF scandata scanclk
/n
t
PFD
Charge Pump
Loop Filter
VCO
/g
t
/m
t
scanaclr
/l
t
/e
t
PLL reconfiguration data is shifted into serial registers from the logic array or external devices. The PLL input shift data uses a reference input shift clock. Once the last bit of the serial chain is clocked in, the register chain is synchronously loaded into the PLL configuration bits. The shift circuitry also provides an asynchronous clear for the serial registers.
Programmable Bandwidth
The designer has advanced control of the PLL bandwidth using the programmable control of the PLL loop characteristics, including loop filter and charge pump. The PLL's bandwidth is a measure of its ability to track the input clock and jitter. A high-bandwidth PLL can quickly lock onto a reference clock and react to any changes in the clock. It also will allow a wide band of input jitter spectrum to pass to the output. A lowbandwidth PLL will take longer to lock, but it will attenuate all highfrequency jitter components. The Quartus II software can adjust PLL characteristics to achieve the desired bandwidth. The programmable bandwidth is tuned by varying the charge pump current, loop filter resistor value, high frequency capacitor value, and m counter value. Designers can manually adjust these values if desired. Bandwidth is programmable from 150 kHz to 2 MHz.
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External Clock Outputs
Enhanced PLLs 5 and 6 each support up to eight single-ended clock outputs (or four differential pairs). See Figure 98. Figure 98. External Clock Outputs for PLLs 5 & 6
From IOE (1) extclk0_a (2)
e0 Counter
From IOE (1) From IOE (1)
extclk0_b
extclk1_a
e1 Counter
4
From IOE (1)
extclk1_b
From IOE (1)
extclk2_a
e2 Counter
extclk2_b From IOE (1) From IOE (1)
extclk3_a
e3 Counter
From IOE (1)
extclk3_b
Notes to Figure 98:
(1) (2) Each external clock output pin can be used as a general purpose output pin from the logic array. These pins are multiplexed with IOE outputs. Two single-ended outputs are possible per output counter--either two outputs of the same frequency and phase or one shifted 180.
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PLLs & Clock Networks
Any of the four external output counters can drive the single-ended or differential clock outputs for PLLs 5 and 6. This means one counter or frequency can drive all output pins available from PLL 5 or PLL 6. Each pair of output pins (four pins total) has dedicated VCC and GND pins to reduce the output clock's overall jitter by providing improved isolation from switching I/O pins. For PLLs 5 and 6, each pin of a single-ended output pair can either be in phase or 180 out of phase. The clock output pin pairs support the same I/O standards as standard output pins (in the top and bottom banks) as well as LVDS, LVPECL, 3.3-V PCML, HyperTransport technology, differential HSTL, and differential SSTL. Table 40 shows which I/O standards the enhanced PLL clock pins support. When in single-ended or differential mode, the two outputs operate off the same power supply. Both outputs use the same standards in single-ended mode to maintain performance. Designers can also use the external clock output pins as user output pins if external enhanced PLL clocking is not needed.
Table 40. I/O Standards Supported for Enhanced PLL Pins (Part 1 of 2) Input I/O Standard INCLK
LVTTL LVCMOS 2.5 V 1.8 V 1.5 V 3.3-V PCI 3.3-V PCI-X LVPECL 3.3-V PCML LVDS HyperTransport technology Differential HSTL Differential SSTL 3.3-V GTL 3.3-V GTL+ 1.5-V HSTL class I 1.5-V HSTL class II SSTL-18 class I SSTL-18 class II v v v v v v v v v v v v v v v v v v v v v v v v
Output PLLENABLE
v v
FBIN
v v v v v v v v v v v
EXTCLK
v v v v v v v v v v v v v v v v v v v
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Table 40. I/O Standards Supported for Enhanced PLL Pins (Part 2 of 2) Input I/O Standard INCLK
SSTL-2 class I SSTL-2 class II SSTL-3 class I SSTL-3 class II AGP (1x and 2x) CTT v v v v v v
Output PLLENABLE EXTCLK
v v v v v v
FBIN
v v v v v v
Enhanced PLLs 11 and 12 support one single-ended output each (see Figure 99). These outputs do not have their own VCC and GND signals. Therefore, to minimize jitter, do not place switching I/O pins next to this output pin. Figure 99. External Clock Outputs for Enhanced PLLs 11 & 12
g0 Counter
CLK13n, I/O, PLL11_OUT or CLK6n, I/O, PLL12_OUT (1)
From Internal Logic or IOE
Note to Figure 99:
(1) For PLL 11, this pin is CLK13n; for PLL 12 this pin is CLK7n.
Stratix GX devices can drive any enhanced PLL driven through the global clock or regional clock network to any general I/O pin as an external output clock. The jitter on the output clock is not guaranteed for these cases.
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PLLs & Clock Networks
Clock Feedback
The following four feedback modes in Stratix GX device enhanced PLLs allow multiplication and/or phase and delay shifting:
Zero delay buffer: The external clock output pin is phase-aligned with the clock input pin for zero delay. External feedback: The external feedback input pin, FBIN, is phase-aligned with the clock input, CLK, pin. Aligning these clocks allows the designer to remove clock delay and skew between devices. This mode is only possible for PLLs 5 and 6. PLLs 5 and 6 each support feedback for one of the dedicated external outputs, either one single-ended or one differential pair. In this mode, one e counter feeds back to the PLL FBIN input, becoming part of the feedback loop. Normal mode: If an internal clock is used in this mode, it is phase-aligned to the input clock pin. The external clock output pin will have a phase delay relative to the clock input pin if connected in this mode. The designer defines which internal clock output from the PLL should be phase-aligned to the internal clock pin. No compensation: In this mode, the PLL will not compensate for any clock networks or external clock outputs.
Phase & Delay Shifting
Stratix GX device enhanced PLLs provide advanced programmable phase and clock delay shifting. For phase shifting, designers can specify a phase shift (in degrees or time units) for each PLL clock output port or for all outputs together in one shift. Phase-shifting values in time units are allowed with a resolution range of 160 to 420 ps. This resolution is a function of frequency input and the multiplication and division factors. In other words, it is a function of the VCO period equal to one-eighth of the VCO period. Each clock output counter can choose a different phase of the VCO period from up to eight taps. Designers can use this clock output counter along with an initial setting on the post-scale counter to achieve a phase-shift range for the entire period of the output clock. The phase tap feedback to the m counter can shift all outputs to a single phase or delay. The Quartus II software automatically sets the phase taps and counter settings according to the phase shift entered.
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In addition to the phase-shift feature, the fine tune clock delay shift feature provides advanced time delay shift control on each of the four PLL outputs. Each PLL output shifts in 250-ps increments for a range of -3.0 ns to +3.0 ns between any two outputs using discrete delay elements. Total delay shift between any two PLL outputs must be less than 3 ns. For example, shifts on outputs of -1 and +2 ns is allowed, but not -1 and +2.5 ns. There is some delay variation due to process, voltage, and temperature. Only the clock delay shift blocks can be controlled during system operation for dynamic clock delay control.
Spread-Spectrum Clocking
The Stratix GX device's enhanced PLLs use spread-spectrum technology to reduce electromagnetic interference generation from a system by distributing the energy over a broader frequency range. The enhanced PLL typically provides 0.5% down spread modulation using a triangular profile. The modulation frequency is programmable. Enabling spread spectrum for a PLL affects all of its outputs.
Lock Detect
The lock output indicates that there is a stable clock output signal in phase with the reference clock. Without any additional circuitry, the lock signal may toggle as the PLL begins tracking the reference clock. Designers may need to gate the lock signal for use as a system control. The lock signal from the locked port can drive the logic array or an output pin. Whenever the PLL loses lock for any reason (be it excessive inclk jitter, clock switchover, PLL reconfiguration, power supply noise etc.), the PLL must be reset with the areset signal for correct phase shift operation. If the phase relationship between the input clock versus output clock, and between different output clocks from the PLL is not important in the design, then the PLL need not be reset.
f
See the Stratix GX FPGA Errata Sheet for more information on implementing the gated lock signal in the design.
Programmable Duty Cycle
The programmable duty cycle allows enhanced PLLs to generate clock outputs with a variable duty cycle. This feature is supported on each enhanced PLL post-scale counter (g0..g3, l0..l3, e0..e3). The duty cycle setting is achieved by a low and high time count setting for the post-scale dividers. The Quartus II software uses the frequency input and the required multiply or divide rate to determine the duty cycle choices.
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PLLs & Clock Networks
Advanced Clear & Enable Control
There are several control signals for clearing and enabling PLLs and their outputs. Designers can use these signals to control PLL resynchronization and gate PLL output clocks for low-power applications. The pllenable pin is a dedicated pin that enables/disables PLLs. When the pllenable pin is low, the clock output ports are driven by GND and all the PLLs go out of lock. When the pllenable pin goes high again, the PLLs relock and resynchronize to the input clocks. Designers can choose which PLLs are controlled by the pllenable signal by connecting the pllenable input port of the altpll megafunction to the common pllenable input pin. The areset signals are reset/resynchronization inputs for each PLL. The areset signal should be asserted every time the PLL loses lock to guarantee correct phase relationship between the PLL output clocks. Users should include the areset signal in designs if any of the following conditions are true:

PLL Reconfiguration or Clock switchover enables in the design. Phase relationships between output clocks need to be maintained after a loss of lock condition
The device input pins or logic elements (LEs) can drive these input signals. When driven high, the PLL counters resets, clearing the PLL output and placing the PLL out of lock. The VCO sets back to its nominal setting (~700 MHz). When driven low again, the PLL resynchronizes to its input as it relocks. If the target VCO frequency is below this nominal frequency, then the output frequency starts at a higher value than desired as the PLL locks. If the system cannot tolerate this, the clkena signal can disable the output clocks until the PLL locks. The pfdena signals control the phase frequency detector (PFD) output with a programmable gate. If designers disable the PFD, the VCO will operate at its last set value of control voltage and frequency with some long-term drift to a lower frequency. The system will continue running when the PLL goes out of lock or the input clock is disabled. By maintaining the last locked frequency, the system has time to store its current settings before shutting down. Designers can either use their own control signal or a clkloss status signal to trigger pfdena.
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The clkena signals control the enhanced PLL regional and global outputs. Each regional and global output port has its own clkena signal. The clkena signals synchronously disable or enable the clock at the PLL output port by gating the outputs of the g and l counters. The clkena signals are registered on the falling edge of the counter output clock to enable or disable the clock without glitches. Figure 100 shows the waveform example for a PLL clock port enable. The PLL can remain locked independent of the clkena signals since the loop-related counters are not affected. This feature is useful for applications that require a low power or sleep mode. Upon re-enabling, the PLL does not need a resynchronization or relock period. The clkena signal can also disable clock outputs if the system is not tolerant to frequency overshoot during resynchronization. The extclkena signals work in the same way as the clkena signals, but they control the external clock output counters (e0, e1, e2, and e3). Upon re-enabling, the PLL does not need a resynchronization or relock period unless the PLL is using external feedback mode. In order to lock in external feedback mode, the external output must drive the board trace back to the FBIN pin. Figure 100. extclkena Signals
COUNTER OUTPUT
CLKENA
CLKOUT
Fast PLLs
Stratix GX devices contain up to four fast PLLs with high-speed serial interfacing ability, along with general-purpose features. Figure 101 shows a diagram of the fast PLL.
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PLLs & Clock Networks
Figure 101. Stratix GX Device Fast PLL
Post-Scale Counters diffioclk1 (2) Global or regional clock txload_en
/l0 VCO Phase Selection Selectable at each PLL Output Port Phase Frequency Detector /l1
rxload_en Global or regional clock diffioclk2 (2)
Global or regional clock (1)
Clock Input
PFD
Charge Pump
Loop Filter
8 VCO
/g0
Global or regional clock
m /
Notes to Figure 101:
(1) (2) In high-speed differential I/O support mode, this high-speed PLL clock feeds the SERDES. Stratix GX devices only support one rate of data transfer per fast PLL in high-speed differential I/O support mode. This signal is a high-speed differential I/O support SERDES control signal.
Clock Multiplication & Division
The Stratix GX device's fast PLLs provide clock synthesis for PLL output ports using m/(post scaler) scaling factors. The input clock is multiplied by the m feedback factor. Each output port has a unique post scale counter to divide down the high-frequency VCO. There is one multiply divider, m, per fast PLL with a range of 1 to 32. There are two post scale L dividers for regional and/or LVDS interface clocks, and g0 counter for global clock output port; all range from 1 to 32. In the case of a high-speed differential interface, the designer can set the output counter to 1 to allow the high-speed VCO frequency to drive the SERDES.
External Clock Outputs
Each fast PLL supports differential or single-ended outputs for source-synchronous transmitters or for general-purpose external clocks. There are no dedicated external clock output pins. Any I/O pin can be driven by the fast PLL global or regional outputs as an external output
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pin. The I/O standards supported by any particular bank determines what standards are possible for an external clock output driven by the fast PLL in that bank. Table 41 shows the I/O standards supported by fast PLL input pins.
Table 41. Fast PLL Port Input Pin I/O Standards Input I/O Standard INCLK
LVTTL LVCMOS 2.5 V 1.8 V 1.5 V 3.3-V PCI 3.3-V PCI-X LVPECL 3.3-V PCML LVDS HyperTransport technology Differential HSTL Differential SSTL 3.3-V GTL 3.3-V GTL+ 1.5V HSTL class I 1.5V HSTL class II SSTL-18 class I SSTL-18 class II SSTL-2 class I SSTL-2 class II SSTL-3 class I SSTL-3 class II AGP (1x and 2x) CTT v v v v v v v v v v v v v v v v v v v v v v
PLLENABLE
v v
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I/O Structure
Phase Shifting
Stratix GX device fast PLLs have advanced clock shift capability that enables programmable phase shifts. Designers can enter a phase shift (in degrees or time units) for each PLL clock output port or for all outputs together in one shift. Designers can perform phase shifting in time units with a resolution range of 150 to 400 ps. This resolution is a function of the VCO period.
Control Signals
The fast PLL has the same lock output, pllenable input, and areset input control signals as the enhanced PLL. For more information on high-speed differential I/O support, see "Source-Synchronous Signaling with DPA" on page 46.
I/O Structure
IOEs provide many features, including:

Dedicated differential and single-ended I/O buffers 3.3-V, 64-bit, 66-MHz PCI compliance 3.3-V, 64-bit, 133-MHz PCI-X 1.0 compliance Joint Test Action Group (JTAG) boundary-scan test (BST) support Differential on-chip termination for LVDS I/O standard Programmable pull-up during configuration Output drive strength control Slew-rate control Tri-state buffers Bus-hold circuitry Programmable pull-up resistors Programmable input and output delays Open-drain outputs DQ and DQS I/O pins Double-data rate (DDR) Registers
The IOE in Stratix GX devices contains a bidirectional I/O buffer, six registers, and a latch for a complete embedded bidirectional single data rate or DDR transfer. Figure 102 shows the Stratix GX IOE structure. The IOE contains two input registers (plus a latch), two output registers, and two output enable registers. The design can use both input registers and the latch to capture DDR input and both output registers to drive DDR outputs. Additionally, the design can use the output enable (OE) register for fast clock-to-output enable timing. The negative edge-clocked OE register is used for DDR SDRAM interfacing. The Quartus II software automatically duplicates a single OE register that controls multiple output or bidirectional pins.
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Figure 102. Stratix GX IOE Structure
Logic Array OE Register OE D Q
OE Register D Q
Output Register Output A D Q
CLK Output Register Output B D Q Input Register D Q
Input A Input B
Input Register D Q
Input Latch D ENA Q
The IOEs are located in I/O blocks around the periphery of the Stratix GX device. There are up to four IOEs per row I/O block and six IOEs per column I/O block. The row I/O blocks drive row, column, or direct link interconnects. The column I/O blocks drive column interconnects. Figure 103 shows how a row I/O block connects to the logic array. Figure 104 shows how a column I/O block connects to the logic array.
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I/O Structure
Figure 103. Row I/O Block Connection to the Interconnect
R4, R8 & R24 Interconnects
C4, C8 & C16 Interconnects
I/O Interconnect I/O Block Local Interconnect 16 Control Signals from I/O Interconnect (1)
16
28 Data & Control Signals from Logic Array (2) 28 Horizontal I/O Block
LAB
io_dataouta[3..0] io_dataoutb[3..0]
Direct Link Interconnect to Adjacent LAB LAB Local Interconnect
Direct Link Interconnect to Adjacent LAB io_clk[7:0]
Horizontal I/O Block Contains up to Four IOEs
Notes to Figure 103:
(1) (2) The 16 control signals are composed of four output enables io_boe[3..0], four clock enables io_bce[3..0], four clocks io_clk[3..0], and four clear signals io_bclr[3..0]. The 28 data and control signals consist of eight data out lines: four lines each for DDR applications io_dataouta[3..0] and io_dataoutb[3..0], four output enables io_coe[3..0], four input clock enables io_cce_in[3..0], four output clock enables io_cce_out[3..0], four clocks io_cclk[3..0], and four clear signals io_cclr[3..0].
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Figure 104. Column I/O Block Connection to the Interconnect
42 Data & Control Signals from Logic Array (2)
Vertical I/O Block
Vertical I/O Block Contains up to Six IOEs
16 Control Signals from I/O Interconnect (1) I/O Block Local Interconnect
16
42 IO_datain[3:0]
io_clk[7..0]
I/O Interconnect
R4, R8 & R24 Interconnects
LAB
LAB
LAB
LAB Local Interconnect
C4, C8 & C16 Interconnects
Notes to Figure 104:
(1) (2) The 16 control signals are composed of four output enables io_boe[3..0], four clock enables io_bce[3..0], four clocks io_bclk[3..0], and four clear signals io_bclr[3..0]. The 42 data and control signals consist of 12 data out lines; six lines each for DDR applications io_dataouta[5..0] and io_dataoutb[5..0], six output enables io_coe[5..0], six input clock enables io_cce_in[5..0], six output clock enables io_cce_out[5..0], six clocks io_cclk[5..0], and six clear signals io_cclr[5..0].
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I/O Structure
Stratix GX devices have an I/O interconnect similar to the R4 and C4 interconnect to drive high-fanout signals to and from the I/O blocks. There are 16 signals that drive into the I/O blocks composed of four output enables io_boe[3..0], four clock enables io_bce[3..0], four clocks io_bclk[3..0], and four clear signals io_bclr[3..0]. The pin's datain signals can drive the IO interconnect, which in turn drives the logic array or other I/O blocks. In addition, the control and data signals can be driven from the logic array, providing a slower but more flexible routing resource. The row or column IOE clocks, io_clk[7..0], provide a dedicated routing resource for low-skew, high-speed clocks. I/O clocks are generated from regional, global, or fast regional clocks (see "PLLs & Clock Networks" on page 129). Figure 105 illustrates the signal paths through the I/O block. Figure 105. Signal Path Through the I/O Block
Row or Column io_clk[7..0] io_boe[3..0] From I/O Interconnect io_bce[3..0] io_bclk[3..0] io_bclr[3..0] To Other IOEs
To Logic Array
io_datain0 io_datain1 oe ce_in ce_out io_coe io_cce_in io_cce_out Control Signal Selection aclr/preset sclr clk_in io_cclr clk_out io_cclk io_dataout0 io_dataout1 IOE
From Logic Array
Each IOE contains its own control signal selection for the following control signals: oe, ce_in, ce_out, aclr/preset, sclr/preset, clk_in, and clk_out. Figure 106 illustrates the control signal selection.
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Figure 106. Control Signal Selection per IOE
io_bclk[3..0] Dedicated I/O Clock [7..0] I/O Interconnect [15..0] Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local Interconnect io_coe io_bce[3..0] io_bclr[3..0] io_boe[3..0]
io_cclr
io_cce_out
io_cce_in
io_cclk
clk_out
ce_out
sclr/preset
clk_in
ce_in
aclr/preset
oe
In normal bidirectional operation, the input register can be used for input data requiring fast setup times. The input register can have its own clock input and clock enable separate from the OE and output registers. The output register can be used for data requiring fast clock-to-output performance. The OE register can be used for fast clock-to-output enable timing. The OE and output register share the same clock source and the same clock enable source from local interconnect in the associated LAB, dedicated I/O clocks, and the column and row interconnects. Figure 107 shows the IOE in bidirectional configuration.
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I/O Structure
Figure 107. Stratix GX IOE in Bidirectional I/O Configuration Note (1)
Column or Row Interconnect ioe_clk[7..0]
I/O Interconnect [15..0]
OE OE Register D clkout ENA CLRN/PRN OE Register tCO Delay VCCIO Q Output tZX Delay
ce_out
Output Enable Clock Enable Delay Output Clock Enable Delay
Optional PCI Clamp
VCCIO
aclr/prn
Programmable Pull-Up Resistor
Chip-Wide Reset Output Register D Q Output Pin Delay Drive Strength Control Open-Drain Output Slew Control Input Pin to Logic Array Delay Input Pin to Input Register Delay
Logic Array to Output Register Delay sclr/preset
ENA CLRN/PRN
Bus-Hold Circuit
Input Register clkin ce_in Input Clock Enable Delay D Q
ENA CLRN/PRN
Note to Figure 107:
(1) All input signals to the IOE can be inverted at the IOE.
The Stratix GX device IOE includes programmable delays that can be activated to ensure zero hold times, input IOE register-to-logic array register transfers, or logic array-to-output IOE register transfers. A path in which a pin directly drives a register may require the delay to ensure zero hold time, whereas a path in which a pin drives a register through combinatorial logic may not require the delay. Programmable delays exist for decreasing input-pin-to-logic-array and IOE input register delays. The Quartus II Compiler can program these delays to automatically minimize setup time while providing a zero hold time.
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Programmable delays can increase the register-to-pin delays for output and/or output enable registers. A programmable delay exists to increase the tZX delay to the output pin, which is required for ZBT interfaces. Table 42 shows the programmable delays for Stratix GX devices.
Table 42. Stratix GX Programmable Delay Chain Programmable Delays
Input pin to logic array delay Input pin to input register delay Output pin delay Output enable register tCO delay Output tZX delay Output clock enable delay Input clock enable delay Logic array to output register delay Output enable clock enable delay
Quartus II Logic Option
Decrease input delay to internal cells Decrease input delay to input register Increase delay to output pin Increase delay to output enable pin Increase tZX delay to output pin Increase output clock enable delay Increase input clock enable delay Decrease input delay to output register Increase output enable clock enable delay
The IOE registers in Stratix GX devices share the same source for clear or preset. The designer can program preset or clear for each individual IOE. The designer can also program the registers to power up high or low after configuration is complete. If programmed to power up low, an asynchronous clear can control the registers. If programmed to power up high, an asynchronous preset can control the registers. This feature prevents the inadvertent activation of another device's active-low input upon power-up. If one register in an IOE uses a preset or clear signal then all registers in the IOE must use that same signal if they require preset or clear. Additionally a synchronous reset signal is available to the designer for the IOE registers.
Double-Data Rate I/O Pins
Stratix GX devices have six registers in the IOE, which support DDR interfacing by clocking data on both positive and negative clock edges. The IOEs in Stratix GX devices support DDR inputs, DDR outputs, and bidirectional DDR modes.
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I/O Structure
When using the IOE for DDR inputs, the two input registers clock double rate input data on alternating edges. An input latch is also used within the IOE for DDR input acquisition. The latch holds the data that is present during the clock high times. This allows both bits of data to be synchronous with the same clock edge (either rising or falling). Figure 108 shows an IOE configured for DDR input. Figure 109 shows the DDR input timing diagram. Figure 108. Stratix GX IOE in DDR Input I/O Configuration Note (1)
Column or Row Interconnect VCCIO ioe_clk[7..0] (1) DQS Local Bus (1), (2) To DQS Local Bus (3)
Optional PCI Clamp
VCCIO
I/O Interconnect [15..0] (1)
Programmable Pull-Up Resistor
Input Pin to Input Register Delay sclr Input Register D clkin ENA CLRN/PRN Q
Output Clock Enable Delay aclr/prn
Bus-Hold Circuit
Chip-Wide Reset Input Register D Q D Latch Q
ENA CLRN/PRN
ENA CLRN/PRN
Notes to Figure 108:
(1) (2) (3) All input signals to the IOE can be inverted at the IOE. This signal connection is only allowed on dedicated DQ function pins. This signal is for dedicated DQS function pins only.
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Figure 109. Input Timing Diagram in DDR Mode
Data at input pin A0 B1 A1 B2 A2 B3 A3 B4
CLK
A'
A1
A2
A3
Input To Logic Array
B' B1 B2 B3
When using the IOE for DDR outputs, the two output registers are configured to clock two data paths from LEs on rising clock edges. These output registers are multiplexed by the clock to drive the output pin at a x2 rate. One output register clocks the first bit out on the clock high time, while the other output register clocks the second bit out on the clock low time. Figure 110 shows the IOE configured for DDR output. Figure 111 shows the DDR output timing diagram.
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I/O Structure
Figure 110. Stratix GX IOE in DDR Output I/O Configuration Notes (1), (2)
Column or Row Interconnect IOE_CLK[7..0]
I/O Interconnect [15..0]
OE Register D clkout ENA CLRN/PRN Output Enable Clock Enable Delay Output Clock Enable Delay aclr/prn VCCIO Q Output tZX Delay
OE Register tCO Delay
Chip-Wide Reset
OE Register D sclr ENA CLRN/PRN Q
Optional PCI Clamp
VCCIO
Used for DDR SDRAM
Programmable Pull-Up Resistor
Logic Array to Output Register Delay
Output Register D Q Output Pin Delay ENA CLRN/PRN clk
Logic Array to Output Register Delay
Output Register D Q
Drive Strength Control Open-Drain Output Slew Control
ENA CLRN/PRN
Bus-Hold Circuit
Notes to Figure 110:
(1) (2) All input signals to the IOE can be inverted at the IOE. The tristate is by default active high. It can, however, be designed to be active low.
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Figure 111. Output Timing Diagram in DDR Mode
CLK
A From Internal Registers B
A1
A2
A3
A4
B1
B2
B3
B4
DDR output
B1
A1
B2
A2
B3
A3
The Stratix GX IOE operates in bidirectional DDR mode by combining the DDR input and DDR output configurations. Stratix GX device I/O pins transfer data on a DDR bidirectional bus to support DDR SDRAM. The negative-edge-clocked OE register holds the OE signal inactive until the falling edge of the clock. This is done to meet DDR SDRAM timing requirements.
External RAM Interfacing
Stratix GX devices support DDR SDRAM at up to 200 MHz (400-Mbps data rate) through dedicated phase-shift circuitry, QDR and QDRII SRAM interfaces up to 167 MHz, and ZBT SRAM interfaces up to 200 MHz. Stratix GX devices also provide preliminary support for reduced latency DRAM II (RLDRAM II) at rates up to 200 MHz through the dedicated phase-shift circuitry. 1 In addition to the required signals for external memory interfacing, Stratix GX devices offer the optional clock enable signal. By default the Quartus II software sets the clock enable signal high, which tells the output register to update with new values. The output registers hold their own values if the design sets the clock enable signal low. See Figure 107.
f
To find out more about the DDR SDRAM specification, see the JEDEC web site (www.jedec.org). For information on memory controller megafunctions for Stratix GX devices, see the Altera web site (www.altera.com). See AN 342: Interfacing DDR SDRAM with Stratix & Stratix GX Devices for more information on DDR SDRAM interface in Stratix GX. Also see AN 349: QDR SRAM Controller Reference Design for Stratix & Stratix GX Devices and AN 329: ZBT SRAM Controller Reference Design for Stratix & Stratix GX Devices.
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Table 43 shows the performance specification for DDR SDRAM, RLDRAM II, QDR SRAM, QDRII SRAM, and ZBT SRAM interfaces in EP1SGX10 through EP1SGX40 devices. The DDR SDRAM and QDR SRAM numbers in Table 43 have been verified with hardware characterization with third-party DDR SDRAM and QDR SRAM devices over temperature and voltage extremes.
Table 43. External RAM Support in EP1SGX10 through EP1SGX40 Devices Maximum Clock Rate (MHz) DDR Memory Type
DDR SDRAM (1), (2) DDR SDRAM - side banks (2), (3), (4) RLDRAM II (4) QDR SRAM (6) QDRII SRAM (6) ZBT SRAM (7) Notes to Table 43:
(1) (2) (3) (4) (5) (6) (7) These maximum clock rates apply if the Stratix GX device uses DQS phase-shift circuitry to interface with DDR SDRAM. DQS phase-shift circuitry is only available in the top and bottom I/O banks (I/O banks 3, 4, 7, and 8). For more information on DDR SDRAM, see AN 342: Interfacing DDR SDRAM with Stratix & Stratix GX Devices. DDR SDRAM is supported on the Stratix GX device side I/O banks (I/O banks 1, 2, 5, and 6) without dedicated DQS phase-shift circuitry. The read DQS signal is ignored in this mode. These performance specifications are preliminary. This device does not support RLDRAM II. For more information on QDR or QDRII SRAM, see AN 349: QDR SRAM Controller Reference Design for Stratix & Stratix GX Devices. For more information on ZBT SRAM, see AN 329: ZBT SRAM Controller Reference Design for Stratix & Stratix GX Devices.
I/O Standard -5 Speed Grade -6 Speed Grade
SSTL-2 SSTL-2 1.8-V HSTL 1.5-V HSTL 1.5-V HSTL LVTTL 200 150 200 167 200 200 167 133 (5) 167 167 200
-7 Speed Grade
133 133 (5) 133 133 167
In addition to six I/O registers and one input latch in the IOE for interfacing to these high-speed memory interfaces, Stratix GX devices also have dedicated circuitry for interfacing with DDR SDRAM. In every Stratix GX device, the I/O banks at the top (I/O banks 3 and 4) and bottom (I/O banks 7 and 8) of the device support DDR SDRAM up to 200 MHz. These pins support DQS signals with DQ bus modes of x8, x16, or x32.
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Table 44 shows the number of DQ and DQS buses that are supported per device.
Table 44. DQS & DQ Bus Mode Support Device
EP1SGX10 EP1SGX25
Note (1) Number of x8 Groups
12 (2) 16 (3) 20 20
Package
672-pin FineLine BGA 672-pin FineLine BGA 1,020-pin FineLine BGA
Number of x16 Groups
0 8 8 8
Number of x32 Groups
0 4 4 4
EP1SGX40
(1) (2) (3)
1,020-pin FineLine BGA
Notes to Table 44:
See the Selectable I/O Standards in Stratix & Stratix GX Devices chapter in the Stratix Device Handbook, Volume 2 for VREF guidelines. These packages have six groups in I/O banks 3 and 4 and six groups in I/O banks 7 and 8. These packages have eight groups in I/O banks 3 and 4 and eight groups in I/O banks 7 and 8.
A compensated delay element on each DQS pin automatically aligns input DQS synchronization signals with the data window of their corresponding DQ data signals. The DQS signals drive a local DQS bus in the top and bottom I/O banks. This DQS bus is an additional resource to the I/O clocks and is used to clock DQ input registers with the DQS signal. Two separate single phase-shifting reference circuits are located on the top and bottom of the Stratix GX device. Each circuit is driven by a system reference clock through the CLK pins that is the same frequency as the DQS signal. Clock pins CLK[15..12]p feed the phase-shift circuitry on the top of the device and clock pins CLK[7..4]p feed the phase-shift circuitry on the bottom of the device. The phase-shifting reference circuit on the top of the device controls the compensated delay elements for all 10 DQS pins located at the top of the device. The phase-shifting reference circuit on the bottom of the device controls the compensated delay elements for all 10 DQS pins located on the bottom of the device. All 10 delay elements (DQS signals) on either the top or bottom of the device shift by the same degree amount. For example, all 10 DQS pins on the top of the device can be shifted by 90 and all 10 DQS pins on the bottom of the device can be shifted by 72. The reference circuits require a maximum of 256 system reference clock cycles to set the correct phase on the DQS delay elements. Figure 112 illustrates the phase-shift reference circuit control of each DQS delay shift on the top of the device. This same circuit is duplicated on the bottom of the device.
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I/O Structure
Figure 112. Simplified Diagram of the DQS Phase-Shift Circuitry
Input Reference Clock
Phase Comparator
Up/Down Counter
Delay Chains
6
Control Signals to DQS Pins
See the External Memory Interfaces chapter in the Stratix Device Handbook, Volume 2 for more information on external memory interfaces.
Programmable Drive Strength
The output buffer for each Stratix GX device I/O pin has a programmable drive strength control for certain I/O standards. The LVTTL and LVCMOS standard has several levels of drive strength that the user can control. SSTL-3 class I and II, SSTL-2 class I and II, HSTL class I and II, and 3.3-V GTL+ support a minimum setting, the lowest drive strength that guarantees the IOH/IOL of the standard. Using minimum settings provides signal slew rate control to reduce system noise and signal overshoot.
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Table 45 shows the possible settings for the I/O standards with drive strength control.
Table 45. Programmable Drive Strength I/O Standard
3.3-V LVTTL 3.3-V LVCMOS 2.5-V LVTTL/LVCMOS 1.8-V LVTTL/LVCMOS 1.5-V LVCMOS GTL/GTL+ 1.5-V HSTL class I and II 1.8-V HSTL class I and II SSTL-3 class I and II SSTL-2 class I and II SSTL-18 class I and II Notes to Table 45:
(1) (2) This is the Quartus II software default current setting. I/O banks 1 and 2 do not support this setting.
IOH / IOL Current Strength Setting (mA)
24 (1), 16, 12, 8, 4 24 (2), 12 (1), 8, 4, 2 16 (1), 12, 8, 2 12 (1), 8, 2 8 (1), 4, 2 Support maximum and minimum strength
The Quartus II software, beginning with version 4.2, will report current strength as "PCI Compliant" for 3.3-V PCI, 3.3-V PCI-X 1.0, and Compact PCI I/O standards. Stratix GX devices support series on-chip termination (OCT) using programmable drive strength. For more information, contact your Altera Support Representative.
Open-Drain Output
Stratix GX devices provide an optional open-drain (equivalent to an open-collector) output for each I/O pin. This open-drain output enables the device to provide system-level control signals (that is, interrupt and write-enable signals) that can be asserted by any of several devices.
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I/O Structure
Slew-Rate Control
The output buffer for each Stratix GX device I/O pin has a programmable output slew-rate control that can be configured for low-noise or highspeed performance. A faster slew rate provides high-speed transitions for high-performance systems. However, these fast transitions may introduce noise transients into the system. A slow slew rate reduces system noise, but adds a nominal delay to rising and falling edges. Each I/O pin has an individual slew-rate control, allowing the designer to specify the slew rate on a pin-by-pin basis. The slew-rate control affects both the rising and falling edges.
Bus Hold
Each Stratix GX device I/O pin provides an optional bus-hold feature. The bus-hold circuitry can weakly hold the signal on an I/O pin at its lastdriven state. Since the bus-hold feature holds the last-driven state of the pin until the next input signal is present, an external pull-up or pull-down resistor is not needed to hold a signal level when the bus is tri-stated. Table 46 shows bus hold support for different pin types.
Table 46. Bus Hold Support Pin Type
I/O pins
Bus Hold v
CLK[15..0] CLK[0,1,2,3,8,9,10,11] FCLK FPLL[7..10]CLK
v
The bus-hold circuitry also pulls undriven pins away from the input threshold voltage where noise can cause unintended high-frequency switching. The designer can select this feature individually for each I/O pin. The bus-hold output will drive no higher than VCCIO to prevent overdriving signals. If the bus-hold feature is enabled, the programmable pull-up option cannot be used. Disable the bus-hold feature when using open-drain outputs with the GTL+ I/O standard or when the I/O pin has been configured for differential signals.
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The bus-hold circuitry uses a resistor with a nominal resistance (RBH) of approximately 7 k to weakly pull the signal level to the last-driven state. Table 4-32 on page 15 gives the specific sustaining current driven through this resistor and overdrive current used to identify the nextdriven input level. This information is provided for each VCCIO voltage level. The bus-hold circuitry is active only after configuration. When going into user mode, the bus-hold circuit captures the value on the pin present at the end of configuration.
Programmable Pull-Up Resistor
Each Stratix GX device I/O pin provides an optional programmable pullup resistor during user mode. If this feature is enabled for an I/O pin, the pull-up resistor (typically 25 k) weakly holds the output to the VCCIO level of the output pin's bank. Table 47 shows which pin types support the weak pull-up resistor feature.
Table 47. Programmable Weak Pull-Up Resistor Support Pin Type
I/O pins
Programmable Weak Pull-Up Resistor v
v
CLK[15..0] FCLK FPLL[7..10]CLK
Configuration pins JTAG pins Note to Table 47:
(1) TDO pins do not support programmable weak pull-up resistors.
v (1)
Advanced I/O Standard Support
Stratix GX device IOEs support the following I/O standards:

LVTTL LVCMOS 1.5 V 1.8 V 2.5 V 3.3-V PCI 3.3-V PCI-X 1.0 3.3-V AGP (1x and 2x)
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LVDS LVPECL 3.3-V PCML HyperTransport Differential HSTL (on input/output clocks only) Differential SSTL (on output column clock pins only) GTL/GTL+ 1.5-V HSTL class I and II 1.8-V HSTL Class I and II SSTL-3 class I and II SSTL-2 class I and II SSTL-18 class I and II CTT
Table 48 describes the I/O standards supported by Stratix GX devices.
Table 48. Stratix GX Supported I/O Standards (Part 1 of 2) Input Reference Voltage (VREF) (V)
N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A 0.75 1.25 0.8 1.0 0.75 0.9 0.90 1.25
I/O Standard
Type
Output Supply Voltage (VCCIO) (V)
3.3 3.3 2.5 1.8 1.5 3.3 3.3 3.3 3.3 3.3 2.5 1.5 2.5 N/A N/A 1.5 1.8 1.8 2.5
Board Termination Voltage (VTT) (V)
N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A 0.75 1.25 1.20 1.5 0.75 0.9 0.90 1.25
LVTTL LVCMOS 2.5 V 1.8 V 1.5 V 3.3-V PCI 3.3-V PCI-X 1.0 LVDS LVPECL 3.3-V PCML HyperTransport Differential HSTL (1) Differential SSTL (2) GTL GTL+ 1.5-V HSTL class I and II 1.8-V HSTL class I and II SSTL-18 class I and II SSTL-2 class I and II
Single-ended Single-ended Single-ended Single-ended Single-ended Single-ended Single-ended Differential Differential Differential Differential Differential Differential Voltage-referenced Voltage-referenced Voltage-referenced Voltage-referenced Voltage-referenced Voltage-referenced
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Table 48. Stratix GX Supported I/O Standards (Part 2 of 2) Input Reference Voltage (VREF) (V)
1.5 1.32 1.5
I/O Standard
Type
Output Supply Voltage (VCCIO) (V)
3.3 3.3 3.3
Board Termination Voltage (VTT) (V)
1.5 N/A 1.5
SSTL-3 class I and II AGP (1x and 2x) CTT Notes to Table 48:
(1) (2)
Voltage-referenced Voltage-referenced Voltage-referenced
This I/O standard is only available on input and output clock pins. This I/O standard is only available on output column clock pins.
f
For more information on I/O standards supported by Stratix GX devices, see the Selectable I/O Standards in Stratix & Stratix GX Devices chapter of the Stratix Device Handbook, Volume 2. Stratix GX devices contain eight I/O banks in addition to the four enhanced PLL external clock out banks, as shown in Figure 113. The four I/O banks on the right and left of the device contain circuitry to support high-speed differential I/O for LVDS, LVPECL, 3.3-V PCML, and HyperTransport inputs and outputs. These banks support all I/O standards listed in Table 48 except PCI I/O pins or PCI-X 1.0, GTL, SSTL18 Class II, and HSTL Class II outputs. The top and bottom I/O banks support all single-ended I/O standards. Additionally, Stratix GX devices support four enhanced PLL external clock output banks, allowing clock output capabilities such as differential support for SSTL and HSTL. Table 49 shows I/O standard support for each I/O bank.
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I/O Structure
Figure 113. Stratix GX I/O Banks Notes (1), (2), (3)
DQST9
PLL7
DQST8
DQST7
Bank 3
DQST6
DQST5 9
VREF1B3 VREF2B3 VREF3B3 VREF4B3 VREF5B3
PLL5 10
DQST4 PLL11
DQST3
DQST2
Bank 4
DQST1
DQST0
VREF1B4 VREF2B4 VREF3B4 VREF4B4 VREF5B4
VREF1B2 VREF2B2 VREF3B2 VREF4B2
I/O Bank 13 (5) LVDS, LVPECL, 3.3-V PCML, and HyperTransport I/O Block and Regular I/O Pins (3)
Bank 2
(4)
I/O Banks 3, 4, 9 & 10 Support All Single-Ended I/O Standards (2)
I/O Bank 14 (5)
PLL1
PLL2 VREF1B1 VREF2B1 VREF3B1 VREF4B1
I/O Banks 1 and 2 Support All Single-Ended I/O Standards Except Differential HSTL Output Clocks, Differential SSTL-2 Output Clocks, HSTL Class II, GTL, SSTL-18 Class II, PCI, PCI-X, and AGP 1x/2x
1.5-V PCML (5)
I/O Bank 17 (5)
Bank 1
(4) LVDS, LVPECL, 3.3-V PCML, and HyperTransport I/O Block and Regular I/O Pins (3)
I/O Banks 7, 8, 11 & 12 Support All Single-Ended I/O Standards (2)
I/O Bank 16 (5)
I/O Bank 15 (5)
Bank 8 11 DQSB6 DQSB5 12 PLL12 DQSB4 DQSB3 Bank 7
VREF5B7 VREF4B7 VREF3B7 VREF2B7 VREF1B7 VREF5B8 VREF4B8 VREF3B8 VREF2B8 VREF1B8
PLL8
DQSB9
DQSB8
DQSB7
PLL6
DQSB2
DQSB1
DQSB0
Notes to Figure 113:
(1) (2) (3) (4) (5) Figure 113 is a top view of the Stratix GX silicon die. Banks 9 through 12 are enhanced PLL external clock output banks. If the high-speed differential I/O pins are not used for high-speed differential signaling, they can support all of the I/O standards except HSTL class I and II, GTL, SSTL-18 Class II, PCI, PCI-X, and AGP 1x/2x. For guidelines for placing single-ended I/O pads next to differential I/O pads, see the Selectable I/O Standards in Stratix & Stratix GX Devices chapter in the Stratix Device Handbook, Volume 2. These I/O banks in Stratix GX devices also support the LVDS, LVPECL, and 3.3-V PCML I/O standards on reference clocks and receiver input pins (AC coupled)
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Table 49 shows I/O standard support for each I/O bank.
Table 49. I/O Support by Bank (Part 1 of 2) I/O Standard
LVTTL LVCMOS 2.5 V 1.8 V 1.5 V 3.3-V PCI 3.3-V PCI-X 1.0 LVPECL 3.3-V PCML LVDS HyperTransport technology Differential HSTL (clock inputs) Differential HSTL (clock outputs) Differential SSTL (clock outputs) 3.3-V GTL 3.3-V GTL+ 1.5-V HSTL class I 1.5-V HSTL class II 1.8-V HSTL class I 1.8-V HSTL class II SSTL-18 class I SSTL-18 class II SSTL-2 class I SSTL-2 class II SSTL-3 class I
Top & Bottom Banks (3, 4, 7 & 8) v v v v v v v
Left Banks (1 & 2) v v v v v
Enhanced PLL External Clock Output Banks (9, 10, 11 & 12) v v v v v v v
v v v v v v
v v v v
v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v
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Table 49. I/O Support by Bank (Part 2 of 2) I/O Standard
SSTL-3 class II AGP (1x and 2x) CTT
Top & Bottom Banks (3, 4, 7 & 8) v v v
Left Banks (1 & 2) v v
Enhanced PLL External Clock Output Banks (9, 10, 11 & 12) v v v
Each I/O bank has its own VCCIO pins. A single device can support 1.5-, 1.8-, 2.5-, and 3.3-V interfaces; each bank can support a different standard independently. Each bank also has dedicated VREF pins to support any one of the voltage-referenced standards (such as SSTL-3) independently. Each I/O bank can support multiple standards with the same VCCIO for input and output pins. Each bank can support one voltage-referenced I/O standard. For example, when VCCIO is 3.3 V, a bank can support LVTTL, LVCMOS, 3.3-V PCI, and SSTL-3 for inputs and outputs.
Differential On-Chip Termination
Stratix GX devices provide differential on-chip termination (LVDS I/O standard) to reduce reflections and maintain signal integrity. Differential on-chip termination simplifies board design by minimizing the number of external termination resistors required. Termination can be placed inside the package, eliminating small stubs that can still lead to reflections. The internal termination is designed using transistors in the linear region of operation. Stratix GX devices support internal differential termination with a nominal resistance value of 137.5 for LVDS input receiver buffers. LVPECL signals require an external termination resistor. Figure 114 shows the device with differential termination.
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Figure 114. LVDS Input Differential On-Chip Termination
Transmitting Device Receiving Device with Differential Termination
Z0
+
RD Z0
+
I/O banks on the left and right side of the device support LVDS receiver (far-end) differential termination. Table 50 shows the Stratix GX device differential termination support.
Table 50. Differential Termination Supported by I/O Banks Differential Termination Support
Differential termination (1), (2) Notes to Table 50:
(1) (2) Clock pin CLK0, CLK2, CLK9, CLK11, and pins FPLL[7..10]CLK do not support differential termination. Differential termination is only supported for LVDS because of a 3.3-V VC C I O .
I/O Standard Support
LVDS
Top & Bottom Banks (3, 4, 7 & 8)
Left Banks (1 & 2)
v
Table 51 shows the termination support for different pin types.
Table 51. Differential Termination Support Across Pin Types Pin Type
Top and bottom I/O banks (3, 4, 7, and 8)
RD
v v
DIFFIO_RX[] CLK[0,2,9,11],CLK[4-7],CLK[12-15] CLK[1,3,8,10] FCLK FPLL[7..10]CLK
The differential on-chip resistance at the receiver input buffer is 118 20 %.
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I/O Structure
However, there is additional resistance present between the device ball and the input of the receiver buffer, as shown in Figure 1. This resistance is because of package trace resistance (which can be calculated as the resistance from the package ball to the pad) and the parasitic layout metal routing resistance (which is shown between the pad and the intersection of the on-chip termination and input buffer). Figure 115. Differential Resistance of LVDS Differential Pin Pair (RD)
Package Ball
0.3 RD
Pad
9.3
LVDS Input Buffer
0.3
9.3
Differential On-Chip Termination Resistor
Package Ball
Pad
Table 52 defines the specification for internal termination resistance for commercial devices.
Table 52. Differential On-Chip Termination Resistance Symbol
RD (2)
Description
Internal differential termination for LVDS
Conditions Min
Commercial (1), (3) Industrial (2), (3) 110 100
Unit Typ
135 135
Max
165 170
Notes to Table 52:
(1) (2) (3) Data measured over minimum conditions (Tj = 0 C, VC C I O +5%) and maximum conditions (Tj = 85 C, VCCIO = -5%). Data measured over minimum conditions (Tj = -40 C, VCCIO +5%) and maximum conditions (Tj = 100 C, VCCIO = -5%). LVDS data rate is supported for 840 Mbps using internal differential termination.
MultiVolt I/O Interface
The Stratix GX architecture supports the MultiVolt I/O interface feature, which allows Stratix GX devices in all packages to interface with systems of different supply voltages. The Stratix GX VCCINT pins must always be connected to a 1.5-V power supply. With a 1.5-V VCCINT level, input pins are 1.5-V, 1.8-V, 2.5-V, and 3.3-V tolerant. The VCCIO pins can be connected to either a 1.5-V, 1.8-V,
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2.5-V, or 3.3-V power supply, depending on the output requirements. The output levels are compatible with systems of the same voltage as the power supply (for example, when VCCIO pins are connected to a 1.5-V power supply, the output levels are compatible with 1.5-V systems). When VCCIO pins are connected to a 3.3-V power supply, the output high is 3.3 V and is compatible with 3.3-V or 5.0-V systems. Table 53 summarizes Stratix GX MultiVolt I/O support.
Table 53. Stratix GX MultiVolt I/O Support Note (1) Input Signal (5) VCCIO (V)
1.5 1.8 2.5 3.3 Notes to Table 53:
(1) (2) (3) (4) (5) (6) To drive inputs higher than VCCIO but less than 4.1 V, disable the PCI clamping diode. However, to drive 5.0-V inputs to the device, enable the PCI clamping diode to prevent VI from rising above 4.0 V. The input pin current may be slightly higher than the typical value. Although VCCIO specifies the voltage necessary for the Stratix GX device to drive out, a receiving device powered at a different level can still interface with the Stratix GX device if it has inputs that tolerate the VCCIO value. Stratix GX devices can be 5.0-V tolerant with the use of an external resistor and the internal PCI clamp diode. This is the external signal that is driving the Stratix GX device. This represents the system voltage that Stratix GX supports when a VCCIO pin is connected to a specific voltage level. For example, when VCCIO is 3.3 V and if the I/O standard is LVTTL/LVCMOS, the output high of the signal coming out from Stratix GX is 3.3 V and is compatible with 3.3-V or 5.0-V systems.
Output Signal (6) 5.0 V 1.5 V v v (3) v (3) v (4) v (3) v v (3) v (3) v v (3) v v 1.8 V 2.5 V 3.3 V 5.0 V
1.5 V v v (2)
1.8 V v v
2.5 V v (2) v (2) v v (2)
3.3 V v (2) v (2) v v
Power Sequencing & Hot Socketing
Because Stratix GX devices can be used in a mixed-voltage environment, they have been designed specifically to tolerate any possible power-up sequence. Therefore, the VCCIO and VCCINT power supplies may be powered in any order. Signals can be driven into Stratix GX devices before and during power up without damaging the device. In addition, Stratix GX devices do not drive out during power up. Once operating conditions are reached and the device is configured, Stratix GX devices operate as specified by the user. For more information, see Hot Socketing in the Selectable I/O Standards in Stratix & Stratix GX Devices chapter in the Stratix Device Handbook, Volume 2.
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IEEE Std. 1149.1 (JTAG) Boundary-Scan Support
IEEE Std. 1149.1 (JTAG) Boundary-Scan Support
All Stratix GX devices provide JTAG BST circuitry that complies with the IEEE Std. 1149.1a-1990 specification. JTAG boundary-scan testing can be performed either before or after, but not during configuration. Stratix GX devices can also use the JTAG port for configuration together with either the Quartus II software or hardware using either Jam Files (.jam) or Jam Byte-Code Files (.jbc). Stratix GX devices support IOE I/O standard setting reconfiguration through the JTAG BST chain. The JTAG chain can update the I/O standard for all input and output pins any time before or during user mode. Designers can use this ability for JTAG testing before configuration when some of the Stratix GX pins drive or receive from other devices on the board using voltage-referenced standards. Because the Stratix GX device may not be configured before JTAG testing, the I/O pins may not be configured for appropriate electrical standards for chip-to-chip communication. Programming those I/O standards via JTAG allows full designers to fully test I/O connection to other devices. The enhanced PLL reconfiguration bits are part of the JTAG chain before configuration and after power-up. After device configuration, the PLL reconfiguration bits are not part of the JTAG chain. Stratix GX devices also use the JTAG port to monitor the logic operation of the device with the SignalTap(R) embedded logic analyzer. Stratix GX devices support the JTAG instructions shown in Table 54.
Table 54. Stratix GX JTAG Instructions (Part 1 of 2) JTAG Instruction Description
normal device operation, and permits an initial data pattern to be output at the device pins. Also used by the SignalTap(R) embedded logic analyzer.
SAMPLE/PRELOAD Allows a snapshot of signals at the device pins to be captured and examined during
EXTEST (1) BYPASS
Allows the external circuitry and board-level interconnects to be tested by forcing a test pattern at the output pins and capturing test results at the input pins. Places the 1-bit bypass register between the TDI and TDO pins, which allows the BST data to pass synchronously through selected devices to adjacent devices during normal device operation. Selects the 32-bit USERCODE register and places it between the TDI and TDO pins, allowing the USERCODE to be serially shifted out of TDO. Selects the IDCODE register and places it between TDI and TDO, allowing the IDCODE to be serially shifted out of TDO. Places the 1-bit bypass register between the TDI and TDO pins, which allows the BST data to pass synchronously through selected devices to adjacent devices during normal device operation, while tri-stating all of the I/O pins.
USERCODE IDCODE HIGHZ (1)
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Table 54. Stratix GX JTAG Instructions (Part 2 of 2) JTAG Instruction
CLAMP (1)
Description
Places the 1-bit bypass register between the TDI and TDO pins, which allows the BST data to pass synchronously through selected devices to adjacent devices during normal device operation while holding I/O pins to a state defined by the data in the boundary-scan register. Used when configuring a Stratix GX device through the JTAG port with a MasterBlasterTM or ByteBlasterMVTM download cable, or when using a .jam file or .jbc file with an embedded processor. Emulates pulsing the nCONFIG pin low to trigger reconfiguration even though the physical pin is unaffected. Allows the IOE standards to be configured through the JTAG chain. Stops configuration if executed during configuration. Can be executed before or after configuration. Monitors internal device operation with the SignalTap embedded logic analyzer.
ICR instructions
PULSE_NCONFIG CONFIG_IO
SignalTap instructions Note to Table 54:
(1)
Bus hold and weak pull-up resistor features override the high-impedance state of HIGHZ, CLAMP, and EXTEST.
The Stratix GX device instruction register length is 10 bits, and the USERCODE register length is 32 bits. Tables 55 and 56 show the boundary-scan register length and IDCODE information for Stratix GX devices.
Table 55. Stratix GX Boundary-Scan Register Length Device
EP1SGX10 EP1SGX25 EP1SGX40
Boundary-Scan Register Length
1,029 1,665 1,941
Table 56. 32-Bit Stratix GX Device IDCODE (Part 1 of 2) IDCODE (32 Bits) (1) Device Version (4 Bits)
EP1SGX10 EP1SGX25
Part Number (16 Bits)
0010 0000 0100 0001 0010 0000 0100 0011
Manufacturer Identity (11 Bits)
000 0110 1110 000 0110 1110
LSB (1 Bit) (2)
1 1
0000 0000
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IEEE Std. 1149.1 (JTAG) Boundary-Scan Support
Table 56. 32-Bit Stratix GX Device IDCODE (Part 2 of 2) IDCODE (32 Bits) (1) Device Version (4 Bits)
EP1SGX40 Notes to Table 56:
(1) (2) The most significant bit (MSB) is at the left end of the string. The IDCODE's least significant bit (LSB) is always 1.
Part Number (16 Bits)
0010 0000 0100 0101
Manufacturer Identity (11 Bits)
000 0110 1110
LSB (1 Bit) (2)
1
0000
Figure 116 shows the timing requirements for the JTAG signals. Figure 116. Stratix GX JTAG Waveforms
TMS
TDI t JCP t JCH TCK tJPZX TDO tJSSU Signal to Be Captured Signal to Be Driven tJSH t JPCO t JPXZ t JCL t JPSU t JPH
tJSZX
tJSCO
tJSXZ
Table 57 shows the JTAG timing parameters and values for Stratix GX devices.
Table 57. Stratix GX JTAG Timing Parameters & Values (Part 1 of 2) Symbol
tJ C P tJ C H tJ C L tJ P S U
Parameter
TCK clock period TCK clock high time TCK clock low time
JTAG port setup time
Min (ns) Max (ns)
100 50 50 20
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Table 57. Stratix GX JTAG Timing Parameters & Values (Part 2 of 2) Symbol
tJ P H tJ P C O tJ P Z X tJ P X Z tJ S S U tJ S H tJ S C O tJ S Z X tJ S X Z
Parameter
JTAG port hold time JTAG port clock to output JTAG port high impedance to valid output JTAG port valid output to high impedance Capture register setup time Capture register hold time Update register clock to output Update register high impedance to valid output Update register valid output to high impedance
Min (ns) Max (ns)
45 25 25 25 20 45 35 35 35
f
For more information on JTAG, see the following documents:

AN 39: IEEE Std. 1149.1 (JTAG) Boundary-Scan Testing in Altera Devices Jam Programming & Test Language Specification
SignalTap Embedded Logic Analyzer
Stratix GX devices feature the SignalTap embedded logic analyzer, which monitors design operation over a period of time through the IEEE Std. 1149.1 (JTAG) circuitry. A designer can analyze internal logic at speed without bringing internal signals to the I/O pins. This feature is particularly important for advanced packages, such as FineLine BGA packages, because it can be difficult to add a connection to a pin during the debugging process after a board is designed and manufactured. The logic, circuitry, and interconnects in the Stratix GX architecture are configured with CMOS SRAM elements. Stratix GX devices are reconfigurable and are 100% tested prior to shipment. As a result, the designer does not have to generate test vectors for fault coverage purposes, and can instead focus on simulation and design verification. In addition, the designer does not need to manage inventories of different ASIC designs. Stratix GX devices can be configured on the board for the specific functionality required. Stratix GX devices are configured at system power-up with data stored in an Altera serial configuration device or provided by a system controller. Altera offers in-system programmability (ISP)-capable configuration devices that configure Stratix GX devices via a serial data stream. Stratix GX devices can be configured in under 100 ms using 8-bit parallel data at 100 MHz. The Stratix GX device's optimized interface allows microprocessors to configure it serially or in parallel, and synchronously
Configuration
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Configuration
or asynchronously. The interface also enables microprocessors to treat Stratix GX devices as memory and configure them by writing to a virtual memory location, making reconfiguration easy. After a Stratix GX device has been configured, it can be reconfigured in-circuit by resetting the device and loading new data. Real-time changes can be made during system operation, enabling innovative reconfigurable computing applications.
Operating Modes
The Stratix GX architecture uses SRAM configuration elements that require configuration data to be loaded each time the circuit powers up. The process of physically loading the SRAM data into the device is called configuration. During initialization, which occurs immediately after configuration, the device resets registers, enables I/O pins, and begins to operate as a logic device. The I/O pins are tri-stated during power up, and before and during configuration. Together, the configuration and initialization processes are called command mode. Normal device operation is called user mode. A built-in weak pull-up resistor pulls all user I/O pins to VCCIO before and during device configuration. SRAM configuration elements allow Stratix GX devices to be reconfigured in-circuit by loading new configuration data into the device. With real-time reconfiguration, the device is forced into command mode with a device pin. The configuration process loads different configuration data, reinitializes the device, and resumes user-mode operation. Designers can perform in-field upgrades by distributing new configuration files either within the system or remotely.
Configuration Schemes
Designers can load the configuration data for a Stratix GX device with one of five configuration schemes (see Table 58), chosen on the basis of the target application. Designers can use a configuration device, intelligent controller, or the JTAG port to configure a Stratix GX device. A configuration device can automatically configure a Stratix GX device at system power-up.
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Multiple Stratix GX devices can be configured in any of five configuration schemes by connecting the configuration enable (nCE) and configuration enable output (nCEO) pins on each device.
Table 58. Data Sources for Configuration Configuration Scheme
Configuration device Passive serial (PS) Passive parallel asynchronous (PPA) Fast passive parallel JTAG
Data Source
Enhanced or EPC2 configuration device ByteBlasterMV or MasterBlaster download cable or serial data source Parallel data source Parallel data source MasterBlaster or ByteBlasterMV download cable or a microprocessor with a Jam or JBC file (.jam or .jbc)
Partial Reconfiguration
The enhanced PLLs within the Stratix GX device family support partial reconfiguration of their multiply, divide, and time delay settings without reconfiguring the entire device. Designers can use either serial data from the logic array or regular I/O pins to program the PLL's counter settings in a serial chain. This option provides considerable flexibility for frequency synthesis, allowing real-time variation of the PLL frequency and delay. The rest of the device is functional while reconfiguring the PLL. See "Enhanced PLLs" on page 143 for more information on Stratix GX PLLs.
Remote Update Configuration Modes
Stratix GX devices also support remote configuration using an Altera enhanced configuration device (for example, EPC16, EPC8, and EPC4 devices) with page mode selection. Factory configuration data is stored in the default page of the configuration device. This is the default configuration which contains the design required to control remote updates and handle or recover from errors. The designer writes the factory configuration once into the flash memory or configuration device. Remote update data can update any of the remaining pages of the configuration device. If there is an error or corruption in a remote update configuration, the configuration device reverts back to the factory configuration information.
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Configuration
There are two remote configuration modes: remote and local configuration. Designers can use the remote update configuration mode for all three configuration modes: serial, parallel synchronous, and parallel asynchronous. Configuration devices (for example, EPC16 devices) only support serial and parallel synchronous modes. Asynchronous parallel mode allows remote updates when an intelligent host is used to configure the Stratix GX device. This host must support page mode settings similar to an EPC16 device.
Remote Update Mode
When the Stratix GX device is first powered-up in remote update programming mode, it loads the configuration located at page address 000. The factory configuration should always be located at page address 000, and should never be remotely updated. The factory configuration contains the required logic to perform the following operations:

Determine the page address/load location for the next application's configuration data Recover from a previous configuration error Receive new configuration data and write it into the configuration device
The factory configuration is the default and takes control if an error occurs while loading the application configuration. While in the factory configuration, the factory-configuration logic performs the following operations:

Loads a remote update-control register to determine the page address of the new application configuration Determines whether to enable a user watchdog timer for the application configuration Determines what the watchdog timer setting should be if it is enabled
The user watchdog timer is a counter that must be continually reset within a specific amount of time in the user mode of an application configuration to ensure that valid configuration occurred during a remote update. Only valid application configurations designed for remote update can reset the user watchdog timer in user mode. If a valid application configuration does not reset the user watchdog timer in a specific amount of time, the timer updates a status register and loads the factory configuration. The user watchdog timer is automatically disabled for factory configurations.
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If an error occurs in loading the application configuration, the configuration logic writes a status register to specify the cause of the reconfiguration. Once this occurs, the Stratix GX device automatically loads the factory configuration, which reads the status register and determines the reason for reconfiguration. Based on the reason, the factory configuration takes appropriate steps and writes the remote update control register to specify the next application configuration page to be loaded. When the Stratix GX device successfully loads the application configuration, it enters into user mode. The Stratix GX device then executes the main application of the user. Intellectual property (IP), such as a Nios(R) embedded processor, can help the Stratix GX device determine when remote update is coming. The Nios embedded processor or user logic receives incoming data, writes it to the configuration device, and loads the factory configuration. The factory configuration will read the remote update status register and determine the valid application configuration to load. Figure 117 shows the Stratix GX remote update. Figure 118 shows the transition diagram for remote update mode. Figure 117. Stratix GX Device Remote Update
Configuration Device
(1)
Watchdog Timer New Remote Configuration Data
Application Configuration Application Configuration
Page 7 Page 6
Stratix GX Device Factory Configuration Configuration Device Updates Stratix GX Device with Factory Configuration (to Handle Update) or New Application Configuration
Page 0
Note to Figure 117:
(1) When the Stratix GX device is configured with the factory configuration, it can handle update data from EPC16, EPC8, or EPC4 configuration device pages and point to the next page in the configuration device.
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Configuration
Figure 118. Remote Update Transition Diagram
Notes (1), (2)
Power-Up
Application 1 Configuration
Configuration Error
Configuration Error
Reload an Application
Factory Configuration
Reload an Application
Configuration Error
Application n Configuration
Notes to Figure 118:
(1) (2) Remote update of application configuration is controlled by a Nios embedded processor or user logic programmed in the factory or application configurations. Up to seven pages can be specified allowing up to seven different configuration applications.
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Local Update Mode
Local update mode is a simplified version of the remote update. This feature is intended for simple systems that need to load a single application configuration immediately upon power-up without loading the factory configuration first. Local update designs have only one application configuration to load, so it does not require a factory configuration to determine which application configuration to use. Figure 119 shows the transition diagram for local update mode. Figure 119. Local Update Transition Diagram
Power-Up or nCONFIG
nCONFIG
Application Configuration
Configuration Error
Configuration Error
nCONFIG
Factory Configuration
Stratix GX Automated Single Event Upset (SEU) Detection
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Stratix GX devices offer on-chip circuitry for automated checking of single event upset (SEU) detection. Some applications that require the device to operate error free at high elevations or in close proximity to earth's North or South Pole will require periodic checks to ensure continued data integrity. The error detection cyclic redundancy code (CRC) feature controlled by the Device & Pin Options dialog box in the Quartus II software uses a 32-bit CRC circuit to ensure data reliability and is one of the best options for mitigating SEU.
Altera Corporation
Temperature-Sensing Diode
Designers can implement the error detection CRC feature with existing circuitry in Stratix GX devices, eliminating the need for external logic. For Stratix GX devices, the CRC is computed by Quartus II and downloaded into the device as a part of the configuration bit stream. The CRC_ERROR pin reports a soft error when configuration SRAM data is corrupted, triggering device reconfiguration.
Custom-Built Circuitry
Dedicated circuitry is built into Stratix GX devices to perform error detection automatically. This error detection circuitry constantly checks for errors in the configuration SRAM cells while the device is in user mode. Designers can monitor one external pin for the error and use it to trigger a reconfiguration cycle. Designers can select the desired time between checks by adjusting a built-in clock divider.
Software Interface
In the Quartus II software version 4.1 and later, designers can turn on the automated error detection CRC feature in the Device & Pin Options dialog box. This dialog box allows designers to enable the feature and set the internal frequency of the CRC between 400 kHz to 100 MHz. This controls the rate that the CRC circuitry verifies the internal configuration SRAM bits in the FPGA device. For more information on CRC, refer to AN 357: Error Detection Using CRC in Altera FPGA Devices.
TemperatureSensing Diode
Stratix GX devices include a diode-connected transistor for use as a temperature sensor in power management. This diode is used with an external digital thermometer device such as a MAX1617A or MAX1619 from MAXIM Integrated Products. These devices steer bias current through the Stratix GX diode, measuring forward voltage and converting this reading to temperature in the form of an 8-bit signed number (7 bits plus sign). The external device's output represents the package temperature of the Stratix GX device and can be used for intelligent power management. The diode requires two pins (tempdiodep and tempdioden) on the Stratix GX device to connect to the external temperature-sensing device, as shown in Figure 120. The temperature-sensing diode is a passive element and therefore can be used before the Stratix GX device is powered.
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Figure 120. External Temperature-Sensing Diode
Stratix GX Device Temperature-Sensing Device
tempdiodep
tempdioden
Table 59 shows the specifications for bias voltage and current of the Stratix GX temperature-sensing diode.
Table 59. Temperature-Sensing Diode Electrical Characteristics Parameter
IB I A S high IB I A S low VB P - VB N VB N Series resistance
Minimum
80 8 0.3
Typical
100 10
Maximum
120 12 0.9
Units
A A V V
0.7 3
W
The temperature-sensing diode works for the entire operating range shown in Figure 121.
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Operating Conditions
Figure 121. Temperature Versus Temperature-Sensing Diode Voltage
0.95 0.90 0.85 0.80 0.75 Voltage (Across Diode) 0.70 0.65 0.60 0.55 0.50 0.45 0.40 -55 -30 -5 20 45 70 95 120 100 A Bias Current 10 A Bias Current
Temperature ( C)
Operating Conditions
Stratix GX devices are offered in both commercial and industrial grades. However, industrial-grade devices may have limited speed-grade availability. Tables 60 through 71 provide information on absolute maximum ratings, recommended operating conditions, DC operating conditions, and transceiver block absolute maximum ratings. Notes for Tables 60 through 65 immediately follow Table 65, notes for Table 66 immediately follow that table, and notes for Tables 67 through 71 immediately follow Table 71.
Table 60. Stratix GX Device Absolute Maximum Ratings (Part 1 of 2) Symbol
VCCINT VCCIO VI IOUT DC input voltage DC output current, per pin
Notes (1), (2) Minimum
-0.5 -0.5 -0.5 -25
Parameter
Supply voltage
Conditions
With respect to ground (3)
Maximum
2.4 4.6 4.6 25
Unit
V V V mA
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Table 60. Stratix GX Device Absolute Maximum Ratings (Part 2 of 2) Symbol
TSTG TAMB TJ
Notes (1), (2) Minimum
-65 -65
Parameter
Storage temperature Ambient temperature Junction temperature No bias
Conditions
Maximum
150 135 135
Unit
C C C
Under bias BGA packages under bias
Table 61. Stratix GX Device Recommended Operating Conditions Symbol
VCCINT VCCIO
Note (7), (12), (13) Minimum
1.425 3.00 (3.135) 2.375 1.71 1.4 -0.5 0
Parameter
Supply voltage for internal logic and input buffers (4)
Conditions
Maximum
1.575 3.60 (3.465) 2.625 1.89 1.6 4.1 VCCIO 85 100
Unit
V V V V V V V C C
Supply voltage for output buffers, (4), (5) 3.3-V operation Supply voltage for output buffers, (4) 2.5-V operation Supply voltage for output buffers, (4) 1.8-V operation Supply voltage for output buffers, (4) 1.5-V operation
VI VO TJ
Input voltage Output voltage Operating junction temperature
(3), (6)
For commercial use For industrial use
0 -40
Table 62. Stratix GX Device DC Operating Conditions Symbol
II IOZ RCONF
Note (12) Minimum
-10 -10 20 30 60
Parameter
Input pin leakage current Tri-stated I/O pin leakage current
Conditions
VI = VC C I O m a x to 0 V (8) VO = VC C I O m a x to 0 V (8)
Typical
Maximum
10 10 50 80 150
Unit
A A k k k
Value of I/O pin pull- VCCIO = 3.0 V (9) up resistor before VCCIO = 2.375 V (9) and during VCCIO = 1.71 V (9) configuration
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Operating Conditions
Table 63. Stratix GX Transceiver Block Absolute Maximum Ratings Symbol
VC C A VC C P VC C R VC C T VC C G Receiver input voltage
Parameter
Transceiver block supply voltage Transceiver block supply voltage Transceiver block supply Voltage Transceiver block supply voltage Transceiver block supply voltage VI C M VO D single / 2 VI C M VO D single / 2
Conditions
Commercial and industrial Commercial and industrial Commercial and industrial Commercial and industrial Commercial and industrial Commercial and industrial Commercial and industrial
Minimum Maximum
-0.5 -0.5 -0.5 -0.5 -0.5 4.6 2.4 2.4 2.4 2.4 1.675 (10), (13) 1.675 (10), (13)
Units
V V V V V V V
refclkb input
voltage
Table 64. Stratix GX Transceiver Block Operating Conditions (Part 1 of 2) Symbol
VC C A VC C P VC C R VC C T VC C G VI D (differential p-p)
Parameter
Transceiver block supply voltage Transceiver block supply voltage Transceiver block supply voltage Transceiver block supply voltage Transceiver block supply voltage Receiver input differential voltage swing
Conditions
Commercial and industrial Commercial and industrial Commercial and industrial Commercial and industrial Commercial and industrial Commercial and industrial Commercial and industrial Commercial and industrial
Minimum
3.135 1.425 1.425 1.425 1.425 170 400 1,025 350
Typical
3.3 1.5 1.5 1.5 1.5
Maximum
3.465 1.575 1.575 1.575 1.575 2,000 2,000
Units
V V V V V mV mV V mV
refclkb input differential voltage swing
VI C M VO D (differential p-p) Receiver input common mode voltage
1,100
1,175 1,600
Transmitter output differential Commercial voltage and industrial
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Table 64. Stratix GX Transceiver Block Operating Conditions (Part 2 of 2) Symbol
VO C M RR E F (11)
Parameter
Transmitter output common mode voltage Reference resistor
Conditions
Commercial and industrial Commercial and industrial
Minimum
Typical
750
Maximum
Units
mV
2K -1%
2K
2K +1%
Table 65. Stratix GX Transceiver Block On-Chip Termination Symbol
Rx
Parameter
Receiver termination
Conditions
Commercial and industrial, 100- setting Commercial and industrial, 120- setting Commercial and industrial, 150- setting
Min
103 120 149 103 120 149 103 120 149
Typ
108 128 158 108 128 158 108 128 158
Max
113 134 167 113 134 167 113 134 167
Units

Tx
Transmitter termination
Commercial and industrial, 100- setting Commercial and industrial, 120- setting Commercial and industrial, 150- setting
Refclkb
Dedicated transceiver clock termination
Commercial and industrial, 100- setting Commercial and industrial, 120- setting Commercial and industrial, 150- setting
Notes to Tables 60 through 65:
(1) (2) (3) See the Operating Requirements for Altera Devices Data Sheet. Conditions beyond those listed in Table 60 may cause permanent damage to a device. Additionally, device operation at the absolute maximum ratings for extended periods of time may have adverse affects on the device. Minimum DC input is -0.5 V. During transitions, the inputs may undershoot to -0.5 V or overshoot to 4.6 V for input currents less than 100 mA and periods shorter than 20 ns. (The information in this note does not include the transceiver pins. See note 13 for information about the transient voltage on the transceiver pins.) Maximum VCC rise time is 100 ms, and VCC must rise monotonically. VCCIO maximum and minimum conditions for LVPECL, LVDS, and 3.3-V PCML are shown in parentheses. All pins, including dedicated inputs, clock, I/O, and JTAG pins, may be driven before VCCINT and VCCIO are powered. Typical values are for TA = 25 C, VCCINT = 1.5 V, and VCCIO = 1.5 V, 1.8 V, 2.5 V, and 3.3 V. This value is specified for normal device operation. The value may vary during power-up. This applies for all VCCIO settings (3.3, 2.5, 1.8, and 1.5 V). Pin pull-up resistance values will lower if an external source drives the pin higher than VCCIO. The device can tolerate prolonged operation at this absolute maximum, as long as the maximum specification is not violated. The DC signal on this pin must be as clean as possible. Ensure that no noise is coupled to this pin. The Stratix GX device's recommended operating conditions do not include the transceiver. Refer to Tables 63 to 66. Minimum DC input to the transceiver pins is -0.5 V. During transitions, the transceiver pins may undershoot to -0.5 V or overshoot to 3.5 V for input currents less than 100 mA and periods shorter than 20 ns.
(4) (5) (6) (7) (8) (9) (10) (11) (12) (13)
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Operating Conditions
Table 66. Stratix GX Transceiver Block AC Specification (Part 1 of 3) -5 Commercial Speed Grade (5) Min
Power per 3.125 Gbps, quadrant 400-mV Vo d (PCS + PMA) 0 pre-
Symbol / Conditions Description
-6 Commercial & Industrial Speed Grade (5) Min Typ
450
-7 Commercial & Industrial Speed Grade (5) Min Typ Max
Unit
Typ
450
Max
Max
mW
emphasis
Dedicated Reference Clock
REFCLK
Jitter tolerance (peak-topeak) Jitter components <20 MHz Wideband
20
20
20
ps
50 25 650 25
50 650 25
50 312.5
ps MHz
REFCLK
(reference input clock frequency)- dedicated
refclkb
pins
REFCLK
(reference input clock frequency)- PLD clock resources
25
325
25
325
25
156.25
MHz
Receiver
Serial data Commercial / rate (general) industrial Serial data rate (8B/10B encoded) Parallel transceiver/ logic array interface speed Rate matching frequency tolerance Receiver total jitter tolerance XAUI mode only Commercial / industrial
614 500
3,187.5 3,187.5
614 500
3,187.5 3,187.5
614 500
2,500 2,500
Mbps Mbps
20
398.4
20
375
20
312.5
MHz
100
100
100
ppm
@ 3.125 Gbps
0.65
0.65
UI
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Table 66. Stratix GX Transceiver Block AC Specification (Part 2 of 3) -5 Commercial Speed Grade (5) Min
Receive sinusoidal jitter tolerance (peak-topeak) f = 22.1 Khz @ 3.125 Gbps f = 1.875 MHz @ 3.125 Gbps f = 20 MHz @ 3.125 Gbps BER Receive latency (2) Single width
Symbol / Conditions Description
-6 Commercial & Industrial Speed Grade (5) Min Typ Max
8.5
-7 Commercial & Industrial Speed Grade (5) Min Typ Max
N/A
Unit
Typ
Max
8.5
UI
0.1
0.1
N/A
UI
0.1 10-12 7 32 7
0.1 10-12 32 7
N/A 10-12 32
UI
Number of parallel clocks Number of parallel clocks UI
Double width
5
19
5
19
5
19
Channel to channel bit skew tolerance (4), (7) Run-length Receiver return loss (differential) Receiver return loss (common mode)
XAUI mode / inter quadrant only
40
40
40
80
100 MHz to 2.5 Ghz 100 MHz to 2.5 Ghz
80 -10
80 -10
UI dB
-10
-6
-6
-6
dB
Transmitter
Serial data rate Parallel transceiver/ core interface speed Serial data output deterministic jitter Serial data output total jitter TDJ @ 3.125 Gbps Commercial / industrial
500 20
3,187.5 398.4
500 20
3,187.5 375
500 20
2500 312.5
Mbps MHz
0.07
0.07
N/A
N/A
N/A
UI
TTJ @ 3.125 Gbps
0.175
0.175
N/A
N/A
N/A
UI
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Operating Conditions
Table 66. Stratix GX Transceiver Block AC Specification (Part 3 of 3) -5 Commercial Speed Grade (5) Min
Jitter transfer Low bandwidth (6) bandwidth setting @ 3.125 Gbps High bandwidth setting @ 3.125 Gbps Low bandwidth setting @ 2.5 Gbps High bandwidth setting @ 2.5 Gbps Output tR I S E Output tFA L L Transmit latency (3) 20%-80% 20%-80% Single width
Symbol / Conditions Description
-6 Commercial & Industrial Speed Grade (5) Min Typ
3
-7 Commercial & Industrial Speed Grade (5) Min Typ Max
N/A
Unit
Typ
3
Max
Max
MHz
4.7
4.7
N/A
MHz
3.2
3.2
3.2
MHz
4.3
4.3
4.3
MHz
60 60 3
130 130 8
60 60 3
130 130 8
60 60 3
130 130 8
ps ps Number of parallel clocks Number of parallel clocks ps
Double width
3
7
3
7
3
7
Intra differential pair skew Channel to Within a channel skew single quadrant Output return loss 100 MHz-2.5 GHz
10
10
10
50
50
50
ps
-10
-10
-10
dB
Notes to Table 66:
(1) (2) (3) (4) (5) (6) (7) UI = Unit Interval. Receive latency delay from serial receiver indata to parallel receiver data. Transmitter latency delay from parallel transceiver data to serial transceiver out data. Per IEEE Standard 802.3ae @ 3.125 for -5 and -6. All numbers for the -6 and -7 speed grades are for both commercial and industrial unless specified otherwise in the Conditions column. Speed grade -5 is available only for commercial specifications. The numbers are for 3.125-Gbps data rate for -5 and -6 devices and 2.5 Gbps for -7 devices. The specification is for channel aligner tolerance.
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Table 67. LVTTL Specifications Symbol
VCCIO VI H VIL VOH VOL
Parameter
Output supply voltage High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage
Conditions
Minimum
3.0 1.7 -0.5
Maximum
3.6 4.1 0.7
Units
V V V V
IOH = -4 to -24 mA (1) IOL = 4 to 24 mA (1)
2.4 0.45
V
Table 68. LVCMOS Specifications Symbol
VCCIO VIH VIL VOH VOL
Parameter
Output supply voltage High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage
Conditions
Minimum
3.0 1.7 -0.5
Maximum
3.6 4.1 0.7
Units
V V V V
VCCIO = 3.0, IOH = -0.1 mA VCCIO = 3.0, IOL = 0.1 mA
VCCIO - 0.2 0.2
V
Table 69. 2.5-V I/O Specifications Symbol
VCCIO VIH VIL VOH
Note (1) Conditions Minimum
2.375 1.7 -0.5 IOH = -0.1 mA IOH = -1 mA IOH = -2 to -16 mA (1) 2.1 2.0 1.7 0.2 0.4 0.7
Parameter
Output supply voltage High-level input voltage Low-level input voltage High-level output voltage
Maximum
2.625 4.1 0.7
Units
V V V V V V V V V
VOL
Low-level output voltage
IOL = 0.1 mA IOH = 1 mA IOH = 2 to 16 mA (1)
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Operating Conditions
Table 70. 1.8-V I/O Specifications Symbol
VCCIO VI H VIL VOH VOL
Parameter
Output supply voltage High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage
Conditions
Minimum
1.65
Maximum
1.95
Units
V V V V
0.65 x VCCIO 2.25 -0.3 IOH = -2 to -8 mA (1) IOL = 2 to 8 mA (1) VCCIO - 0.45 0.45 0.35 x VCCIO
V
Table 71. 1.5-V I/O Specifications Symbol
VCCIO VI H VIL VOH VOL
(1)
Parameter
Output supply voltage High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage
Conditions
Minimum
1.4
Maximum
1.6
Units
V V V V
0.65 x VCCIO VCCIO + 0.3 -0.3 IOH = -2 mA (1) IOL = 2 mA (1) 0.75 x VCCIO 0.25 x VCCIO 0.35 x VCCIO
V
Note to Tables 67 through 71:
Drive strength is programmable according to values in Table 45 on page 172.
Figures 122 and 123 show receiver input and transmitter output waveforms, respectively, for all differential I/O standards (LVDS, 3.3-V PCML, LVPECL, and HyperTransport technology).
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Figure 122. Receiver Input Waveforms for Differential I/O Standards
Single-Ended Waveform Positive Channel (p) = VIH VID Negative Channel (n) = VIL VCM Ground
Differential Waveform
VID p-n=0V VID
Figure 123. Transmitter Output Waveforms for Differential I/O Standards
Single-Ended Waveform Positive Channel (p) = VOH VOD Negative Channel (n) = VOL VCM Ground
Differential Waveform
VOD p-n=0V VOD
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Operating Conditions
Tables 72 through 92 provide information about specifications and bus hold parameters for 1.5-V Stratix GX devices. Notes for Tables 73 through 92 immediately follow Table 92.
Table 72. 3.3-V LVDS I/O Specifications Symbol
VCCIO VI D (1)
Parameter
I/O supply voltage Input differential voltage swing (single-ended)
Conditions
Minimum
3.135
Typical
3.3
Maximum
3.465 1,000 1,000 1,000 1,000 1,100
Units
V mV mV mV mV mV
0.1 V < VC M < 1.1 V W = 1 through 10 1.1 V < VC M < 1.6 V W=1 1.1 V < VC M < 1.6 V W = 2 through 10 1.6 V < VC M < 1.8 V W = 1 through 10
300 200 100 300 100
VI C M (1)
Input common-mode voltage
LVDS 0.3 V < VI D < 1.0 V W = 1 through 10 LVDS 0.3 V < VI D < 1.0 V W = 1 through 10 LVDS 0.2 V < VI D < 1.0 V W=1 LVDS 0.1 V < VI D < 1.0 V W = 2 through 10
1,600
1,800
mV
1,100
1,600
mV
1,100
1,600
mV
VOD VOD VOCM VOCM RL
Differential output voltage Change in VOD between high and low Output common-mode voltage Change in VOCM between high and low Receiver differential input resistor, external
RL = 100 RL = 100 RL = 100 RL = 100
250
375
550 50
mV mV mV mV
1,125
1,200
1,375 50
90
100
110
Note to Table 72:
(1) For up to 1 Gbps in DPA mode and 840 Mbps in non-DPA mode
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Table 73. 3.3-V PCML Specifications Symbol
VCCIO VID VICM VOD VOD VO C M VO C M VT R1 R2
Parameter
I/O supply voltage Input differential voltage swing (single-ended) Input common mode voltage Output differential voltage (single-ended) Change in VO D between high and low Output common mode voltage Change in VO C M between high and low Output termination voltage Output external pull-up resistors Output external pull-up resistors
Conditions
Minimum
3.135 300 1.5 300
Typical
3.3
Maximum
3.465 600 3.465
Units
V mV V mV mV V mV V
370
500 50
2.5
2.85
3.3 50
VC C I O 45 45 50 50 55 55
W W
Table 74. LVPECL Specifications Symbol
VCCIO VID VICM VOD VO C M RL
Parameter
I/O supply voltage Input differential voltage swing (single-ended) Input common mode voltage Differential output voltage Output common mode voltage Receiver differential input resistor, external
Conditions
Minimum
3.135 300 1
Typical
3.3
Maximum
3.465 1,000 2
Units
V mV V mV mV W
RL = 100 RL = 100
525 1.5 90
700 1.7 100
970 1.9 110
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Operating Conditions
Table 75. HyperTransport Specifications Symbol
VCCIO VOD VO D VOCM VO C M VID VICM RL
Parameter
I/O supply voltage Differential output voltage Change in between high and low Output common mode voltage Change in between high and low Differential input voltage swing (single-ended) Input common mode voltage Receiver differential input resistor, external
Conditions
RL = 100 RL = 100 RL = 100 RL = 100
Minimum
2.375 380
Typical
2.5 485
Maximum
2.625 820 50
Units
V mV mV mV mV mV mV W
440
650
780 50
300 300 90 100
900 900 110
Table 76. 3.3-V PCI Specifications Symbol
VCCIO VIH VIL VOH VOL
Parameter
Output supply voltage High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage
Conditions
Minimum
3.0 0.5 x VCCIO -0.5
Typical
3.3
Maximum
3.6 VCCIO + 0.5 0.3 x VCCIO
Units
V V V V
IOUT = -500 A IOUT = 1,500 A
0.9 x VCCIO 0.1 x VCCIO
V
Table 77. PCI-X Specifications (Part 1 of 2) Symbol
VCCIO VIH VIL VIPU
Parameter
Output supply voltage High-level input voltage Low-level input voltage Input pull-up voltage
Conditions
Minimum
3.0 0.5 x VCCIO -0.5 0.7 x VCCIO
Typical
Maximum
3.6 VCCIO + 0.5 0.35 x VCCIO
Units
V V V V
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Table 77. PCI-X Specifications (Part 2 of 2) Symbol
VO H VO L
Parameter
High-level output voltage Low-level output voltage
Conditions
IO U T = -500 A IO U T = 1,500 A
Minimum
0.9 x VC C I O
Typical
Maximum
Units
V
0.1 x VC C I O
V
Table 78. GTL+ I/O Specifications Symbol
VTT VREF VIH VIL VOL
Parameter
Termination voltage Reference voltage High-level input voltage Low-level input voltage Low-level output voltage
Conditions
Minimum
1.35 0.88 VREF + 0.1
Typical
1.5 1.0
Maximum
1.65 1.12
Units
V V V
VR E F - 0.1 IOL = 36 mA (1) 0.65
V V
Table 79. GTL I/O Specifications Symbol
VTT VREF VIH VIL VOL
Parameter
Termination voltage Reference voltage High-level input voltage Low-level input voltage Low-level output voltage
Conditions
Minimum
1.14 0.74 VREF + 0.05
Typical
1.2 0.8
Maximum
1.26 0.86
Units
V V V
VR E F - 0.05 IOL = 40 mA (1) 0.4
V V
Table 80. SSTL-18 Class I Specifications (Part 1 of 2) Symbol
VCCIO VREF VTT VIH(DC) VIL(DC)
Parameter
Output supply voltage Reference voltage Termination voltage High-level DC input voltage Low-level DC input voltage
Conditions
Minimum
1.65 0.8 VR E F - 0.04 VR E F + 0.125
Typical
1.8 0.9 VR E F
Maximum
1.95 1.0 VR E F + 0.04
Units
V V V V
VR E F - 0.125
V
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Operating Conditions
Table 80. SSTL-18 Class I Specifications (Part 2 of 2) Symbol
VIH(AC) VIL(AC) VOH VOL
Parameter
High-level AC input voltage Low-level AC input voltage High-level output voltage Low-level output voltage
Conditions
Minimum
VR E F + 0.275
Typical
Maximum
Units
V
VR E F - 0.275 IOH = -6.7 mA (1) IOL = 6.7 mA (1) VTT + 0.475 VT T - 0.475
V V V
Table 81. SSTL-18 Class II Specifications Symbol
VCCIO VREF VTT VIH(DC) VIL(DC) VIH(AC) VIL(AC) VOH VOL
Parameter
Output supply voltage Reference voltage Termination voltage High-level DC input voltage Low-level DC input voltage High-level AC input voltage Low-level AC input voltage High-level output voltage Low-level output voltage
Conditions
Minimum
1.65 0.8 VR E F - 0.04 VR E F + 0.125
Typical
1.8 0.9 VR E F
Maximum
1.95 1.0 VR E F + 0.04
Units
V V V V
VR E F - 0.125 VR E F + 0.275 VR E F - 0.275 IOH = -13.4 mA (1) IOL = 13.4 mA (1) VTT + 0.630 VT T - 0.630
V V V V V
Table 82. SSTL-2 Class I Specifications (Part 1 of 2) Symbol
VCCIO VTT VREF VIH VIL
Parameter
Output supply voltage Termination voltage Reference voltage High-level input voltage Low-level input voltage
Conditions
Minimum
2.375 VR E F - 0.04 1.15 VR E F + 0.18 -0.3
Typical
2.5 VR E F 1.25
Maximum
2.625 VR E F + 0.04 1.35 3.0 VR E F - 0.18
Units
V V V V V
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Table 82. SSTL-2 Class I Specifications (Part 2 of 2) Symbol
VOH VOL
Parameter
High-level output voltage Low-level output voltage
Conditions
IOH = -8.1 mA (1) IOL = 8.1 mA (1)
Minimum
VTT + 0.57
Typical
Maximum
Units
V
VT T - 0.57
V
Table 83. SSTL-2 Class II Specifications Symbol
VCCIO VTT VREF VIH VIL VOH VOL
Parameter
Output supply voltage Termination voltage Reference voltage High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage
Conditions
Minimum
2.3 VR E F - 0.04 1.15 VR E F + 0.18 -0.3
Typical
2.5 VR E F 1.25
Maximum
2.7 VR E F + 0.04 1.35 VCCIO + 0.3 VR E F - 0.18
Units
V V V V V V
IOH = -16.4 mA (1) IOL = 16.4 mA (1)
VTT + 0.76 VT T - 0.76
V
Table 84. SSTL-3 Class I Specifications Symbol
VCCIO VTT VREF VIH VIL VOH VOL
Parameter
Output supply voltage Termination voltage Reference voltage High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage
Conditions
Minimum
3.0
Typical
3.3
Maximum
3.6 VR E F + 0.05 1.7 VCCIO + 0.3 VR E F - 0.2
Units
V V V V V V
VR E F - 0.05 VR E F 1.3 VR E F + 0.2 -0.3 IOH = -8 mA (1) IOL = 8 mA (1) VTT + 0.6 1.5
VT T - 0.6
V
Table 85. SSTL-3 Class II Specifications (Part 1 of 2) Symbol
VCCIO VTT VREF VIH
Parameter
Output supply voltage Termination voltage Reference voltage High-level input voltage
Conditions
Minimum
3.0
Typical
3.3
Maximum
3.6 VR E F + 0.05 1.7 VCCIO + 0.3
Units
V V V V
VR E F - 0.05 VR E F 1.3 VR E F + 0.2 1.5
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Operating Conditions
Table 85. SSTL-3 Class II Specifications (Part 2 of 2) Symbol
VIL VOH VOL
Parameter
Low-level input voltage High-level output voltage Low-level output voltage
Conditions
Minimum
-0.3
Typical
Maximum
VR E F - 0.2
Units
V V
IOH = -16 mA (1) VT T + 0.8 IOL = 16 mA (1) VT T - 0.8
V
Table 86. 3.3-V AGP 2x Specifications Symbol
VCCIO VREF VIH VIL VOH VOL
Parameter
Output supply voltage Reference voltage High-level input voltage (2) Low-level input voltage (2) High-level output voltage Low-level output voltage
Conditions
Minimum
3.15 0.39 x VC C I O 0.5 x VC C I O
Typical
3.3
Maximum
3.45 0.41 x VC C I O VCCIO + 0.5 0.3 x VC C I O
Units
V V V V V V
IOUT = -0.5 mA IOUT = 1.5 mA
0.9 x VC C I O
3.6 0.1 x VC C I O
Table 87. 3.3-V AGP 1x Specifications Symbol
VCCIO VIH VIL VOH VOL
Parameter
Output supply voltage High-level input voltage (2) Low-level input voltage (2) High-level output voltage Low-level output voltage
Conditions
Minimum
3.15 0.5 x VC C I O
Typical
3.3
Maximum
3.45 VCCIO + 0.5 0.3 x VC C I O
Units
V V V V V
IOUT = -0.5 mA IOUT = 1.5 mA
0.9 x VC C I O
3.6 0.1 x VC C I O
Table 88. 1.5-V HSTL Class I Specifications (Part 1 of 2) Symbol
VCCIO VREF VTT VIH (DC) VIL (DC) VIH (AC) VIL (AC)
Parameter
Output supply voltage Input reference voltage Termination voltage DC high-level input voltage DC low-level input voltage AC high-level input voltage AC low-level input voltage
Conditions
Minimum
1.4 0.68 0.7 VR E F + 0.1 -0.3 VR E F + 0.2
Typical
1.5 0.75 0.75
Maximum
1.6 0.9 0.8
Units
V V V V
VR E F - 0.1
V V
VR E F - 0.2
V
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Table 88. 1.5-V HSTL Class I Specifications (Part 2 of 2) Symbol
VOH VOL
Parameter
High-level output voltage Low-level output voltage
Conditions
IO H = 8 mA (1) IO H = -8 mA (1)
Minimum
VC C I O - 0.4
Typical
Maximum
Units
V
0.4
V
Table 89. 1.5-V HSTL Class II Specifications Symbol
VCCIO VREF VTT VIH (DC) VIL (DC) VIH (AC) VIL (AC) VOH VOL
Parameter
Output supply voltage Input reference voltage Termination voltage DC high-level input voltage DC low-level input voltage AC high-level input voltage AC low-level input voltage High-level output voltage Low-level output voltage
Conditions
Minimum
1.4 0.68 0.7 VR E F + 0.1 -0.3 VR E F + 0.2
Typical
1.5 0.75 0.75
Maximum
1.6 0.9 0.8
Units
V V V V
VR E F - 0.1
V V
VR E F - 0.2 IOH = 16 mA (1) IO H = -16 mA (1) VC C I O - 0.4 0.4
V V V
Table 90. 1.5-V Differential HSTL Specifications Symbol
VCCIO VDIF (DC) VCM (DC) VDIF (AC)
Parameter
I/O supply voltage DC input differential voltage DC common mode input voltage AC differential input voltage
Conditions
Minimum
1.4 0.2 0.68 0.4
Typical
1.5
Maximum
1.6
Units
V V
0.9
V V
Table 91. CTT I/O Specifications (Part 1 of 2) Symbol
VCCIO VT T /VREF VIH VIL
Parameter
Output supply voltage Termination and input reference voltage High-level input voltage Low-level input voltage
Conditions
Minimum
3.0 1.35 VR E F + 0.2
Typical
3.3 1.5
Maximum
3.6 1.65
Units
V V V
VR E F - 0.2
V
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Power Consumption
Table 91. CTT I/O Specifications (Part 2 of 2) Symbol
VOH VOL IO
Parameter
High-level output voltage Low-level output voltage Output leakage current (when output is high Z)
Conditions
IOH = -8 mA IOL = 8 mA GND VO U T VC C I O
Minimum
VR E F + 0.4
Typical
Maximum
Units
V
VR E F - 0.4 -10 10
V A
Table 92. Bus Hold Parameters VC C I O Level Parameter Conditions 1.5 V Min
Low sustaining current VIN > VIL (maximum) 25 -25 160 -160 0.5 1.0 0.68
1.8 V Min
30 -30 200 -200 1.07 0.7
2.5 V Min
50 -50 300 -300 1.7 0.8
3.3 V Min
70 -70 500 -500 2.0
Units
Max
Max
Max
Max
A A A A V
High sustaining VIN < VIH current (minimum) Low overdrive current High overdrive current Bus-hold trip point Notes to Tables 73 through 92:
(1) (2)
0 V < VIN < VCCIO 0 V < VIN < VCCIO
Drive strength is programmable according to values in Table 45 on page 172. VR E F specifies the center point of the switching range.
Power Consumption Timing Model
Detailed power consumption information for Stratix GX devices will be released when available.
The DirectDrive technology and MultiTrack interconnect ensure predictable performance, accurate simulation, and accurate timing analysis across all Stratix GX device densities and speed grades. This section describes and specifies the performance, internal, external, and PLL timing specifications. All specifications are representative of worst-case supply voltage and junction temperature conditions.
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Preliminary & Final Timing
Timing models can have either preliminary or final status. The Quartus II software displays an informational message during the design compilation if the timing models are preliminary. Table 93 shows the status of the Stratix GX device timing models. Preliminary status means the timing model is subject to change. Initially, timing numbers are created using simulation results, process data, and other known parameters. These tests are used to make the preliminary numbers as close to the actual timing parameters as possible. Final timing numbers are based on actual device operation and testing. These numbers reflect the actual performance of the device under worstcase voltage and junction temperature conditions.
Table 93. Stratix GX Device Timing Model Status Device
EP1SGX10 EP1SGX25 EP1SGX40
Preliminary
-- -- --
Final
v v v
Performance
Table 94 shows Stratix GX performance for some common designs. All performance values were obtained with Quartus II software compilation of LPM, or MegaCore functions for the FIR and FFT designs.
Table 94. Stratix Performance (Part 1 of 3) Notes (1), (2) Resources Used Applications TriMatrix -5 DSP LEs Memory Speed Blocks Blocks Grade
22 46 16 64 0 30 0 0 0 0 1 1 0 0 0 0 0 0 407.83 318.26 422.11 321.85 317.76 319.18
Performance -6 Speed Grade
324.56 255.29 422.11 290.52 277.62 278.86
-7 Speed Grade
288.68 242.89 390.01 261.23 241.48 242.54
Units
MHz MHz MHz MHz MHz MHz
LE
16-to-1 multiplexer (1) 32-to-1 multiplexer (3) 16-bit counter 64-bit counter
Simple dual-port RAM 32 x 18 TriMatrix bit memory M512 block FIFO 32 x 18 bit
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Timing Model
Table 94. Stratix Performance (Part 2 of 3) Notes (1), (2) Resources Used Applications TriMatrix -5 DSP LEs Memory Speed Blocks Blocks Grade
0 0 34 1 0 0 1 1 1 1 1 1 0 0 0 0 0 0 290.86 290.86 290.86 255.95 255.95 255.95
Performance -6 Speed Grade
255.55 255.55 255.55 223.06 233.06 233.06
-7 Speed Grade
222.27 222.27 222.27 194.06 194.06 194.06
Units
MHz MHz MHz MHz MHz MHz
TriMatrix memory M4K block
Simple dual-port RAM 128 x 36 bit True dual-port RAM 128 x 18 bit FIFO 128 x 36 bit
TriMatrix memory M-RAM block
Single port RAM 4K x 144 bit Simple dual-port RAM 4K x 144 bit True dual-port RAM 4K x 144 bit Single port RAM 8K x 72 bit Simple dual-port RAM 8K x 72 bit True dual-port RAM 8K x 72 bit Single port RAM 16K x 36 bit Simple dual-port RAM 16K x 36 bit
0 0
1 1
0 0
278.94 255.95
243.19 223.06
211.59 194.06
MHz MHz
0
1
0
255.95
223.06
194.06
MHz
0 0
1 1
0 0
280.66 269.83
254.32 237.69
221.28 206.82
MHz MHz
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Table 94. Stratix Performance (Part 3 of 3) Notes (1), (2) Resources Used Applications TriMatrix -5 DSP LEs Memory Speed Blocks Blocks Grade
0 1 0 269.83
Performance -6 Speed Grade
237.69
-7 Speed Grade
206.82
Units
MHz
TriMatrix memory M-RAM block
True dual-port RAM 16K x 36 bit Single port RAM 32K x 18 bit Simple dual-port RAM 32K x 18 bit True dual-port RAM 32K x 18 bit Single port RAM 64K x 9 bit Simple dual-port RAM 64K x 9 bit True dual-port RAM 64K x 9 bit
0 0
1 1
0 0
275.86 275.86
244.55 244.55
212.76 212.76
MHz MHz
0
1
0
275.86
244.55
212.76
MHz
0 0
1 1
0 0
287.85 287.85
253.29 253.29
220.36 220.36
MHz MHz
0
1
0
287.85
253.29
220.36
MHz
DSP block
9 x 9-bit multiplier (3) 18 x 18-bit multiplier (4) 36 x 36-bit multiplier (4) 36 x 36-bit multiplier (5) 18-bit, 4-tap FIR filter
0 0 0 0 0 58 870
0 0 0 0 0 0 5
1 1 1 1 1 4 1
335.0 278.78 148.25 278.78 278.78 141.26 261.09
293.94 237.41 134.71 237.41 237.41 133.49 235.51
255.68 206.52 117.16 206.52 206.52 114.88 205.21
MHz MHz MHz MHz MHz MHz MHz
Larger Designs
8-bit, 16-tap parallel FIR filter 8-bit, 1,024-point FFT function
Notes to Table 94:
(1) (2) (3) (4) (5) These design performance numbers were obtained using the Quartus II software. Numbers not listed will be included in a future version of the data sheet. This application uses registered inputs and outputs. This application uses registered multiplier input and output stages within the DSP block. This application uses registered multiplier input, pipeline, and output stages within the DSP block.
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Timing Model
Internal Timing Parameters
Internal timing parameters are specified on a speed grade basis independent of device density. Tables 95 through 101 describe the Stratix GX device internal timing microparameters for LEs, IOEs, TriMatrix memory structures, DSP blocks, and MultiTrack interconnects.
Table 95. LE Internal Timing Microparameter Descriptions Symbol
tSU tH tCO tLUT tCLR tPRE tCLKHL
Parameter
LE register setup time before clock LE register hold time after clock LE register clock-to-output delay LE combinational LUT delay for data-in to data-out Minimum clear pulse width Minimum preset pulse width Minimum clock high or low time
Table 96. IOE Internal Timing Microparameter Descriptions Symbol
tSU tH tCO tPIN2COMBOUT_R tPIN2COMBOUT_C tCOMBIN2PIN_R tCOMBIN2PIN_C tCLR tPRE tCLKHL
Parameter
IOE input and output register setup time before clock IOE input and output register hold time after clock IOE input and output register clock-to-output delay Row input pin to IOE combinational output Column input pin to IOE combinational output Row IOE data input to combinational output pin Column IOE data input to combinational output pin Minimum clear pulse width Minimum preset pulse width Minimum clock high or low time
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Table 97. DSP Block Internal Timing Microparameter Descriptions Symbol
tSU tH tCO tINREG2PIPE9 tINREG2PIPE18 tPIPE2OUTREG2ADD tPIPE2OUTREG4ADD tPD9 tPD18 tPD36 tCLR tCLKHL
Parameter
Input, pipeline, and output register setup time before clock Input, pipeline, and output register hold time after clock Input, pipeline, and output register clock-to-output delay Input register to DSP block pipeline register in 9 x 9-bit mode Input register to DSP block pipeline register in 18 x 18-bit mode DSP block pipeline register to output register delay in twomultipliers adder mode DSP Block Pipeline Register to output register delay in fourmultipliers adder mode Combinational input to output delay for 9 x 9-bit mode Combinational input to output delay for 18 x 18-bit mode Combinational input to output delay for 36 x 36-bit mode Minimum clear pulse width Minimum clock high or low time
Table 98. M512 Block Internal Timing Microparameter Descriptions Symbol
tM512RC tM512WC tM512WERESU tM512WEREH tM512DATASU tM512DATAH tM512WADDRSU tM512WADDRH tM512RADDRSU tM512RADDRH tM512DATACO1 tM512DATACO2 tM512CLKHL tM512CLR
Parameter
Synchronous read cycle time Synchronous write cycle time Write or read enable setup time before clock Write or read enable hold time after clock Data setup time before clock Data hold time after clock Write address setup time before clock Write address hold time after clock Read address setup time before clock Read address hold time after clock Clock-to-output delay when using output registers Clock-to-output delay without output registers Minimum clock high or low time Minimum clear pulse width
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Timing Model
Table 99. M4K Block Internal Timing Microparameter Descriptions Symbol
tM4KRC tM4KWC tM4KWERESU tM4KWEREH tM4KBESU tM4KBEH tM4KDATAASU tM4KDATAAH tM4KADDRASU tM4KADDRAH tM4KDATABSU tM4KDATABH tM4KADDRBSU tM4KADDRBH tM4KDATACO1 tM4KDATACO2 tM4KCLKHL tM4KCLR
Parameter
Synchronous read cycle time Synchronous write cycle time Write or read enable setup time before clock Write or read enable hold time after clock Byte enable setup time before clock Byte enable hold time after clock A port data setup time before clock A port data hold time after clock A port address setup time before clock A port address hold time after clock B port data setup time before clock B port data hold time after clock B port address setup time before clock B port address hold time after clock Clock-to-output delay when using output registers Clock-to-output delay without output registers Minimum clock high or low time Minimum clear pulse width
Table 100. M-RAM Block Internal Timing Microparameter Descriptions (Part 1 of 2) Symbol
tMRAMRC tMRAMWC tMRAMWERESU tMRAMWEREH tMRAMBESU tMRAMBEH tMRAMDATAASU tMRAMDATAAH tMRAMADDRASU tMRAMADDRAH
Parameter
Synchronous read cycle time Synchronous write cycle time Write or read enable setup time before clock Write or read enable hold time after clock Byte enable setup time before clock Byte enable hold time after clock A port data setup time before clock A port data hold time after clock A port address setup time before clock A port address hold time after clock
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Table 100. M-RAM Block Internal Timing Microparameter Descriptions (Part 2 of 2) Symbol
tMRAMDATABSU tMRAMDATABH tMRAMADDRBSU tMRAMADDRBH tMRAMDATACO1 tMRAMDATACO2 tMRAMCLKHL tMRAMCLR
Parameter
B port setup time before clock B port hold time after clock B port address setup time before clock B port address hold time after clock Clock-to-output delay when using output registers Clock-to-output delay without output registers Minimum clock high or low time Minimum clear pulse width
Table 101. Routing Delay Internal Timing Microparameter Descriptions Symbol
tR4 tR8 tR24 tC4 tC8 tC16 tLOCAL
Parameter
Delay for an R4 line with average loading; covers a distance of four LAB columns Delay for an R8 line with average loading; covers a distance of eight LAB columns Delay for an R24 line with average loading; covers a distance of 24 LAB columns Delay for an C4 line with average loading; covers a distance of four LAB rows Delay for an C8 line with average loading; covers a distance of eight LAB rows Delay for an C16 line with average loading; covers a distance of 16 LAB rows Local interconnect delay
Table 102. Stratix GX Reset & PLL Lock Time Parameter Descriptions (Part 1 of 2) Symbol
tA N A L O G R E S E T P W tD I G I T A L R E S E T P W tT X _ P L L _ L O C K
Parameter
Pulse width to power down analog circuits. Pulse width to reset digital circuits The time it takes the tx_pll to lock to the reference clock.
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Timing Model
Table 102. Stratix GX Reset & PLL Lock Time Parameter Descriptions (Part 2 of 2) Symbol
tR X _ F R E Q L O C K tRX_FREQLOCK2PHASELOCK
Parameter
The time until the clock recovery unit (CRU) switches to data mode from lock to reference mode. The time until CRU phase locks to data after switching from lock to data mode.
Figure 124 shows the TriMatrix memory waveforms for the M512, M4K, and M-RAM timing parameters shown in Tables 98 through 100 above. Figure 124. Dual-Port RAM Timing Microparameter Waveform
wrclock tWEREH wren tWADDRSU wraddress an-1 tDATAH data-in din-1 tDATASU rdclock tWERESU rden tRC rdaddress bn b0 tDATACO1 reg_data-out doutn-2 doutn-1 tDATACO2 unreg_data-out doutn-1 doutn dout0 doutn dout0 b1 b2 b3 tWEREH din din4 din5 din6 an a0 a1 a2 a3 a4 tWADDRH a5 a6 tWERESU
Altera Corporation
221 Preliminary
Stratix GX FPGA Family
Figure 125. Stratix GX Transceiver Reset & PLL Lock Time Waveform Note (1)
Reset Signals pll_areset rx_analogreset tx_digitalreset rx_digitalreset Output Status Signals pll_locked rx_freqlocked Ttx_pll_lock Trx_freqlock CRU Phase Locked to Data Trx_freqlock2phaselock TdigitalresetPW TanalogresetPW
Note to Figure 125:
(1) Waveforms are for minimum pulse width timing and output timing only. Please refer to the Stratix GX User's Guide for the complete reset sequence.
Tables 103 through 109 show the internal timing microparameters for all Stratix GX devices.
Table 103. LE Internal Timing Microparameters -5 Speed Grade -6 Speed Grade -7 Speed Grade Symbol Min
tSU tH tCO tLUT tCLR tPRE tCLKHL 100 100 100 10 100 156 366 100 100 100
Unit Max Min
10 100 176 459 114 114 114
Max
Min
11 114
Max
ns ns 202 527 ns ns ns ns ns
222 Preliminary
Altera Corporation
Timing Model
Table 104. IOE Internal Timing Microparameters -5 Speed Grade -6 Speed Grade -7 Speed Grade Symbol Min
tSU tH tCO tPIN2COMBOUT_R tPIN2COMBOUT_C tCOMBIN2PIN_R tCOMBIN2PIN_C tCLR tPRE tCLKHL 262 262 90 64 76 162 1,038 927 2,944 3,189 276 276 95
Unit Max Min
68 80 171 1,093 976 3,099 3,357 317 317 109
Max
Min
68 80
Max
ns ns 171 1,256 1,122 3,563 3,860 ns ns ns ns ns ns ns ns
Table 105. DSP Block Internal Timing Microparameters -5 Speed Grade Min
tSU tH tCO tINREG2PIPE18 tINREG2PIPE9 tPIPE2OUTREG2ADD tPIPE2OUTREG4ADD tPD9 tPD18 tPD36 tCLR tCLKHL 450 1,350 0 67 142 2,613 3,390 2,002 2,899 3,709 4,795 7,495 500 1,500
Symbol
-6 Speed Grade Min
0 75 158 2,982 3,993 2,203 3,189 4,081 5,275 8,245
-7 Speed Grade Min
0 86 181 3,429 4,591 2,533 3,667 4,692 6,065 9,481 575 1,724
Unit
ns ns ns ns ns ns ns ns ns ns ns ns
Max
Max
Max
Altera Corporation
223 Preliminary
Stratix GX FPGA Family
Table 106. M512 Block Internal Timing Microparameters -5 Speed Grade -6 Speed Grade -7 Speed Grade Symbol Min
tM512RC tM512WC tM512WERESU tM512WERH tM512DATASU tM512DATAH tM512WADDRASU tM512WADDRH tM512DATACO1 tM512DATACO2 tM512CLKHL tM512CLR 150 170 110 34 110 34 110 34 424 3,366 167 189
Unit Max
3,340 3,318 123 38 123 38 123 38 472 3,846 192 217
Min
Max
3,816 3,590
Min
Max
4,387 4,128 ns ns ns ns ns ns ns ns 541 4,421 ns ns ns ns
141 43 141 43 141 43
Table 107. M4K Block Internal Timing Microparameters (Part 1 of 2) -5 Speed Grade Symbol Min
tM4KRC tM4KWC tM4KWERESU tM4KWERH tM4KDATASU tM4KDATAH tM4KWADDRASU tM4KWADDRH tM4KRADDRASU tM4KRADDRH tM4KDATABSU tM4KDATABH tM4KADDRBSU tM4KADDRBH 131 34 131 34 131 34 131 34 131 34 131 34
-6 Speed Grade Min Max
4,320 2,840 149 38 149 38 149 38 149 38 149 38 149 38
-7 Speed Grade Unit Min Max
4,967 3,265 171 43 171 43 171 43 171 43 171 43 171 43 ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Max
3,807 2,556
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Altera Corporation
Timing Model
Table 107. M4K Block Internal Timing Microparameters (Part 2 of 2) -5 Speed Grade Symbol Min
tM4KDATACO1 tM4KDATACO2 tM4KCLKHL tM4KCLR 150 170
-6 Speed Grade Min Max
635 4,507 167 189
-7 Speed Grade Unit Min Max
729 5,182 192 255 ns ns ns ns
Max
571 3,984
Table 108. M-RAM Block Internal Timing Microparameters -5 Symbol Min
tMRAMRC tMRAMWC tMRAMWERESU tMRAMWERH tMRAMDATASU tMRAMDATAH tMRAMWADDRASU tMRAMWADDRH tMRAMRADDRASU tMRAMRADDRH tMRAMDATABSU tMRAMDATABH tMRAMADDRBSU tMRAMADDRBH tMRAMDATACO1 tMRAMDATACO2 tMRAMCLKHL tMRAMCLR 270 135 25 18 25 18 25 18 25 18 25 18 25 18 1,038 4,362 300 150
-6 Max
4,364 3,654 25 20 25 20 25 20 25 20 25 20 25 20 1,053 4,939 345 172
-7 Unit Max
4,838 4,127 28 23 28 23 28 23 28 23 28 23 28 23 1,210 5,678
Min
Min
Max
5,562 4,746 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Altera Corporation
225 Preliminary
Stratix GX FPGA Family
Table 109. Stratix GX Transceiver Reset & PLL Lock Time Parameters Symbol
tA N A L O G R E S E T P W (5) tD I G I TA L R E S E T P W (5) tT X _ P L L _ L O C K (3) tR X _ F R E Q L O C K (4) tR X _ F R E Q L O C K 2 P H A S E L O C K (2) Notes to Table 109:
(1) (2) (3) (4) (5) The minimum pulse width specified is associated with the power-down of circuits. The clock recovery unit (CRU) phase locked-to-data time is based on a data rate of 500 Mbps and 8B/10B encoded data. After #pll_areset, pll_enable, or PLL power-up, the time required for the transceiver PLL to lock to the reference clock. After #rx_analogreset, the time for the CRU to switch to lock-to-data mode. There is no maximum pulse width specification. The GXB can be held in reset indefinitely.
Min
1 4
Typ
Max
mS
Units
Parallel clock cycle 10 5 2 S mS mS
Routing delays vary depending on the load on a specific routing line. The Quartus II software reports the routing delay information when running the timing analysis for a design. Contact Altera Applications Engineering for more details.
External Timing Parameters
External timing parameters are specified by device density and speed grade. Figure 126 shows the timing model for bidirectional IOE pin timing. All registers are within the IOE.
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Altera Corporation
Timing Model
Figure 126. External Timing in Stratix GX Devices
OE Register D PRN Q tINSU tINH tOUTCO
Dedicated Clock
CLRN Output Register D PRN Q Bidirectional Pin
CLRN
Input Register PRN D Q
CLRN
All external I/O timing parameters shown are for 3.3-V LVTTL or LVCMOS I/O standards with the maximum current strength. For external I/O timing using standards other than LVTTL or LVCMOS use the I/O standard input and output delay adders in Tables 131 through 135. Table 110 shows the external I/O timing parameters when using fast regional clock networks.
Table 110. Stratix GX Fast Regional Clock External I/O Timing Parameters Symbol
tINSU tINH tOUTCO
Notes (1), (2) Conditions
Parameter
Setup time for input or bidirectional pin using column IOE input register with fast regional clock fed by FCLK pin Hold time for input or bidirectional pin using column IOE input register with fast regional clock fed by FCLK pin Clock-to-output delay output or bidirectional pin using column IOE output register with fast regional clock fed by FCLK pin
CL O A D = 10 pF
Notes to Table 110:
(1) (2) These timing parameters are sample-tested only. These timing parameters are for column IOE pins. Row IOE pins are 100- to 250-ps slower depending on device and speed grade and whether it is tCO or tSU. Designers should use the Quartus II software to verify the external timing for any pin.
Altera Corporation
227 Preliminary
Stratix GX FPGA Family
Table 111 shows the external I/O timing parameters when using regional clock networks.
Table 111. Stratix GX Regional Clock External I/O Timing Parameters Symbol
tINSU tINH tOUTCO
Notes (1), (2) Conditions
Parameter
Setup time for input or bidirectional pin using column IOE input register with regional clock fed by CLK pin Hold time for input or bidirectional pin using column IOE input register with regional clock fed by CLK pin Clock-to-output delay output or bidirectional pin using column IOE output register with regional clock fed by CLK pin Setup time for input or bidirectional pin using column IOE input register with regional clock fed by Enhanced PLL with default phase setting Hold time for input or bidirectional pin using column IOE input register with regional clock fed by Enhanced PLL with default phase setting Clock-to-output delay output or bidirectional pin using column IOE output register with regional clock Enhanced PLL with default phase setting
CL O A D = 10 pF
tINSUPLL
tINHPLL
tOUTCOPLL
CL O A D = 10 pF
Notes to Table 111:
(1) (2) These timing parameters are sample-tested only. These timing parameters are for column IOE pins. Row IOE pins are 100- to 250-ps slower depending on device, speed grade, and the specific parameter in question. Designers should use the Quartus II software to verify the external timing for any pin.
Table 112 shows the external I/O timing parameters when using global clock networks.
Table 112. Stratix GX Global Clock External I/O Timing Parameters (Part 1 of 2) Symbol
tINSU tINH tOUTCO tINSUPLL
Notes (1), (2) Conditions
Parameter
Setup time for input or bidirectional pin using column IOE input register with global clock fed by CLK pin Hold time for input or bidirectional pin using column IOE input register with global clock fed by CLK pin
CL O A D = 10 pF Clock-to-output delay output or bidirectional pin using column IOE output register with global clock fed by CLK pin Setup time for input or bidirectional pin using column IOE input register with global clock fed by Enhanced PLL with default phase setting
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Altera Corporation
Timing Model
Table 112. Stratix GX Global Clock External I/O Timing Parameters (Part 2 of 2) Symbol
tINHPLL
Notes (1), (2) Conditions
Parameter
Hold time for input or bidirectional pin using column IOE input register with global clock fed by enhanced PLL with default phase setting Clock-to-output delay output or bidirectional pin using column IOE output register with global clock enhanced PLL with default phase setting
tOUTCOPLL
CL O A D = 10 pF
Notes to Table 112:
(1) (2) These timing parameters are sample-tested only. These timing parameters are for column IOE pins. Row IOE pins are 100- to 250-ps slower depending on device, speed grade, and the specific parameter in question. Designers should use the Quartus II software to verify the external timing for any pin.
Tables 113 through 118 show the external timing parameters on column and row pins for EP1SGX10 devices.
Table 113. EP1SGX10 Column Pin Fast Regional Clock External I/O Timing Parameters -5 Speed Grade Symbol Min
tINSU tINH tOUTCO 2.245 0.000 2.000 4.597
-6 Speed Grade Min
2.332 0.000 2.000 4.920
-7 Speed Grade Unit Min
2.666 0.000 2.000 5.635
Max
Max
Max
ns ns ns
Table 114. EP1SGX10 Column Pin Regional Clock External I/O Timing Parameters -5 Speed Grade Symbol Min
tINSU tINH tOUTCO tINSUPLL tINHPLL tOUTCOPLL 2.114 0.000 2.000 1.035 0.000 0.500 2.629 4.728
-6 Speed Grade Min
2.218 0.000 2.000 0.941 0.000 0.500 2.769 5.078
-7 Speed Grade Unit Min
2.348 0.000 2.000 1.070 0.000 0.500 3.158 6.004
Max
Max
Max
ns ns ns ns ns ns
Altera Corporation
229 Preliminary
Stratix GX FPGA Family
Table 115. EP1SGX10 Column Pin Global Clock External I/O Timing Parameters -5 Speed Grade Symbol Min
tINSU tINH tOUTCO tINSUPLL tINHPLL tOUTCOPLL 1.785 0.000 2.000 0.988 0.000 0.500 2.634 5.057
-6 Speed Grade Min
1.814 0.000 2.000 0.936 0.000 0.500 2.774 5.438
-7 Speed Grade Unit Min
2.087 0.000 2.000 1.066 0.000 0.500 3.162 6.214
Max
Max
Max
ns ns ns ns ns ns
Table 116. EP1SGX10 Row Pin Fast Regional Clock External I/O Timing Parameters -5 Speed Grade Symbol Min
tINSU tINH tOUTCO 2.194 0.000 2.000 4.956
-6 Speed Grade Min
2.384 0.000 2.000 4.971
-7 Speed Grade Unit Min
2.727 0.000 2.000 5.463
Max
Max
Max
ns ns ns
Table 117. EP1SGX10 Row Pin Regional Clock External I/O Timing Parameters -5 Speed Grade Symbol Min
tINSU tINH tOUTCO tINSUPLL tINHPLL tOUTCOPLL 2.244 0.000 2.000 1.126 0.000 0.500 2.804 4.906
-6 Speed Grade Min
2.413 0.000 2.000 1.186 0.000 0.500 2.627 4.942
-7 Speed Grade Unit Min
2.574 0.000 2.000 1.352 0.000 0.500 2.765 5.616
Max
Max
Max
ns ns ns ns ns ns
Table 118. EP1SGX10 Row Pin Global Clock External I/O Timing Parameters (Part 1 of 2) -5 Speed Grade Symbol Min
tINSU tINH 1.919 0.000
-6 Speed Grade Min
2.062 0.000
-7 Speed Grade Unit Min
2.368 0.000
Max
Max
Max
ns ns
230 Preliminary
Altera Corporation
Timing Model
Table 118. EP1SGX10 Row Pin Global Clock External I/O Timing Parameters (Part 2 of 2) -5 Speed Grade Symbol Min
tOUTCO tINSUPLL tINHPLL tOUTCOPLL 2.000 1.126 0.000 0.500 2.804
-6 Speed Grade Min
2.000 1.186 0.000 0.500 2.627
-7 Speed Grade Unit Min
2.000 1.352 0.000 0.500 2.765
Max
5.231
Max
5.293
Max
5.822 ns ns ns ns
Tables 119 through 124 show the external timing parameters on column and row pins for EP1SGX25 devices.
Table 119. EP1SGX25 Column Pin Fast Regional Clock External I/O Timing Parameters -5 Speed Grade Symbol Min
tINSU tINH tOUTCO 2.418 0.000 2.000 4.524
-6 Speed Grade Min
2.618 0.000 2.000 4.834
-7 Speed Grade Unit Min
3.014 0.000 2.000 5.538
Max
Max
Max
ns ns ns
Table 120. EP1SGX25 Column Pin Regional Clock External I/O Timing Parameters -5 Speed Grade Symbol Min
tINSU tINH tOUTCO tINSUPLL tINHPLL tOUTCOPLL 1.713 0.000 2.000 1.061 0.000 0.500 2.661 5.229
-6 Speed Grade Min
1.838 0.000 2.000 1.155 0.000 0.500 2.799 5.614
-7 Speed Grade Unit Min
2.069 0.000 2.000 1.284 0.000 0.500 3.195 6.432
Max
Max
Max
ns ns ns ns ns ns
Altera Corporation
231 Preliminary
Stratix GX FPGA Family
Table 121. EP1SGX25 Column Pin Global Clock External I/O Timing Parameters -5 Speed Grade Symbol Min
tINSU tINH tOUTCO tINSUPLL tINHPLL tOUTCOPLL 1.790 0.000 2.000 1.046 0.000 0.500 2.676 5.194
-6 Speed Grade Min
1.883 0.000 2.000 1.141 0.000 0.500 2.813 5.569
-7 Speed Grade Unit Min
2.120 0.000 2.000 1.220 0.000 0.500 3.208 6.381
Max
Max
Max
ns ns ns ns ns ns
Table 122. EP1SGX25 Row Pin Fast Regional Clock External I/O Timing Parameters -5 Speed Grade Symbol Min
tINSU tINH tOUTCO 2.394 0.000 2.000 4.456
-6 Speed Grade Min
2.594 0.000 2.000 4.761
-7 Speed Grade Unit Min
2.936 0.000 2.000 5.454
Max
Max
Max
ns ns ns
Table 123. EP1SGX25 Row Pin Regional Clock External I/O Timing Parameters -5 Speed Grade Symbol Min
tINSU tINH tOUTCO tINSUPLL tINHPLL tOUTCOPLL 1.970 0.000 2.000 1.326 0.000 0.500 2.304 4.880
-6 Speed Grade Min
2.109 0.000 2.000 1.386 0.000 0.500 2.427 5.246
-7 Speed Grade Unit Min
2.377 0.000 2.000 1.552 0.000 0.500 2.765 6.013
Max
Max
Max
ns ns ns ns ns ns
Table 124. EP1SGX25 Row Pin Global Clock External I/O Timing Parameters (Part 1 of 2) -5 Speed Grade Symbol Min
tINSU tINH 1.963 0.000
-6 Speed Grade Min
2.108 0.000
-7 Speed Grade Unit Min
2.379 0.000
Max
Max
Max
ns ns
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Altera Corporation
Timing Model
Table 124. EP1SGX25 Row Pin Global Clock External I/O Timing Parameters (Part 2 of 2) -5 Speed Grade Symbol Min
tOUTCO tINSUPLL tINHPLL tOUTCOPLL 2.000 1.326 0.000 0.500 2.304
-6 Speed Grade Min
2.000 1.386 0.000 0.500 2.427
-7 Speed Grade Unit Min
2.000 1.552 0.000 0.500 2.765
Max
4.887
Max
5.247
Max
6.011 ns ns ns ns
Tables 125 through 130 show the external timing parameters on column and row pins for EP1SGX40 devices.
Table 125. EP1SGX40 Column Pin Fast Regional Clock External I/O Timing Parameters -5 Speed Grade Symbol Min
tINSU tINH tOUTCO 2.704 0.000 2.000 5.060
-6 Speed Grade Min
2.912 0.000 2.000 5.432
-7 Speed Grade Unit Min
3.235 0.000 2.000 6.226
Max
Max
Max
ns ns ns
Table 126. EP1SGX40 Column Pin Regional Clock External I/O Timing Parameters -5 Speed Grade Symbol Min
tINSU tINH tOUTCO tINSUPLL tINHPLL tOUTCOPLL 2.467 0.000 2.000 1.254 0.000 0.500 2.610 5.255
-6 Speed Grade Min
2.671 0.000 2.000 1.259 0.000 0.500 2.751 5.673
-7 Speed Grade Unit Min
3.011 0.000 2.000 1.445 0.000 0.500 3.134 6.501
Max
Max
Max
ns ns ns ns ns ns
Altera Corporation
233 Preliminary
Stratix GX FPGA Family
Table 127. EP1SGX40 Column Pin Global Clock External I/O Timing Parameters -5 Speed Grade Symbol Min
tINSU tINH tOUTCO tINSUPLL tINHPLL tOUTCOPLL 2.033 0.000 2.000 1.228 0.000 0.500 2.594 5.689
-6 Speed Grade Min
2.184 0.000 2.000 1.278 0.000 0.500 2.732 6.116
-7 Speed Grade Unit Min
2.451 0.000 2.000 1.415 0.000 0.500 3.113 7.010
Max
Max
Max
ns ns ns ns ns ns
Table 128. EP1SGX40 Row Pin Fast Regional Clock External I/O Timing Parameters -5 Speed Grade Symbol Min
tINSU tINH tOUTCO 2.450 0.000 2.000 4.880
-6 Speed Grade Min
2.662 0.000 2.000 5.241
-7 Speed Grade Unit Min
3.046 0.000 2.000 6.004
Max
Max
Max
ns ns ns
Table 129. EP1SGX40 Row Pin Regional Clock External I/O Timing Parameters -5 Speed Grade Symbol Min
tINSU tINH tOUTCO tINSUPLL tINHPLL tOUTCOPLL 2.398 0.000 2.000 1.126 0.000 0.500 2.304 4.932
-6 Speed Grade Min
2.567 0.000 2.000 1.186 0.000 0.500 2.427 5.336
-7 Speed Grade Unit Min
2.938 0.000 2.000 1.352 0.000 0.500 2.765 6.112
Max
Max
Max
ns ns ns ns ns ns
Table 130. EP1SGX40 Row Pin Global Clock External I/O Timing Parameters (Part 1 of 2) -5 Speed Grade Symbol Min
tINSU tINH 1.965 0.000
-6 Speed Grade Min
2.128 0.000
-7 Speed Grade Unit Min
2.429 0.000
Max
Max
Max
ns ns
234 Preliminary
Altera Corporation
Timing Model
Table 130. EP1SGX40 Row Pin Global Clock External I/O Timing Parameters (Part 2 of 2) -5 Speed Grade Symbol Min
tOUTCO tINSUPLL tINHPLL tOUTCOPLL 2.000 1.126 0.000 0.500 2.304
-6 Speed Grade Min
2.000 1.186 0.000 0.500 2.427
-7 Speed Grade Unit Min
2.000 1.352 0.000 0.500 2.765
Max
5.365
Max
5.775
Max
6.621 ns ns ns ns
External I/O Delay Parameters
External I/O delay timing parameters, both for I/O standard input and output adders and programmable input and output delays, are specified by speed grade, independent of device density. Tables 131 through 136 show the adder delays associated with column and row I/O pins. If an I/O standard is selected other than LVTTL 24 mA with a fast slew rate, add the selected delay to the external tCO and tSU I/O parameters.
Table 131. Stratix GX I/O Standard Column Pin Input Delay Adders (Part 1 of 2) -5 Speed Grade I/O Standard Min
LVCMOS 3.3-V LVTTL 2.5-V LVTTL 1.8-V LVTTL 1.5-V LVTTL GTL GTL+ 3.3-V PCI 3.3-V PCI-X 1.0 Compact PCI AGP 1x AGP 2x CTT SSTL-3 class I SSTL-3 class II
-6 Speed Grade Min Max
0 0 31 157 220 231 231 0 0 0 0 0 126 -32 -32
-7 Speed Grade Unit Min Max
0 0 35 180 252 265 265 0 0 0 0 0 144 -37 -37 ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps
Max
0 0 30 150 210 220 220 0 0 0 0 0 120 -30 -30
Altera Corporation
235 Preliminary
Stratix GX FPGA Family
Table 131. Stratix GX I/O Standard Column Pin Input Delay Adders (Part 2 of 2) -5 Speed Grade I/O Standard Min
SSTL-2 class I SSTL-2 class II SSTL-18 class I SSTL-18 class II 1.5-V HSTL class I 1.5-V HSTL class II 1.8-V HSTL class I 1.8-V HSTL class II
-6 Speed Grade Min Max
-74 -74 189 189 126 126 73 73
-7 Speed Grade Unit Min Max
-86 -86 217 217 144 144 83 83 ps ps ps ps ps ps ps ps
Max
-70 -70 180 180 120 120 70 70
Table 132. Stratix GX I/O Standard Row Pin Input Delay Adders (Part 1 of 2) -5 Speed Grade I/O Standard Min
LVCMOS 3.3-V LVTTL 2.5-V LVTTL 1.8-V LVTTL 1.5-V LVTTL GTL GTL+ 3.3-V PCI 3.3-V PCI-X 1.0 Compact PCI AGP 1x AGP 2x CTT SSTL-3 class I SSTL-3 class II SSTL-2 class I SSTL-2 class II SSTL-18 class I SSTL-18 class II 1.5-V HSTL class I
-6 Speed Grade Min Max
0 0 31 157 220 0 231 0 0 0 0 0 84 -32 -32 -74 -74 189 0 136
-7 Speed Grade Unit Min Max
0 0 35 180 252 0 265 0 0 0 0 0 96 -37 -37 -86 -86 217 0 156 ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps
Max
0 0 30 150 210 0 220 0 0 0 0 0 80 -30 -30 -70 -70 180 0 130
236 Preliminary
Altera Corporation
Timing Model
Table 132. Stratix GX I/O Standard Row Pin Input Delay Adders (Part 2 of 2) -5 Speed Grade I/O Standard Min
1.5-V HSTL class II 1.8-V HSTL class I 1.8-V HSTL class II LVDS (1) LVPECL (1) 3.3-V PCML (1) HyperTransport (1)
-6 Speed Grade Min Max
0 73 73 42 -53 346 84
-7 Speed Grade Unit Min Max
0 83 83 48 -61 397 96 ps ps ps ps ps ps ps
Max
0 70 70 40 -50 330 80
Table 133. Stratix GX I/O Standard Output Delay Adders for Fast Slew Rate on Column Pins (Part 1 of 2) -5 Speed Grade Standard Min
LVCMOS 2 mA 4 mA 8 mA 12 mA 24 mA 3.3-V LVTTL 4 mA 8 mA 12 mA 16 mA 24 mA 2.5-V LVTTL 2 mA 8 mA 12 mA 16 mA 1.8-V LVTTL 2 mA 8 mA 12 mA 1.5-V LVTTL 2 mA 4 mA 8 mA GTL
-6 Speed Grade Min Max
599 599 368 137 0 599 368 137 74 0 872 263 147 105 441 368 368 1,827 1,218 725 -157
-7 Speed Grade Unit Min Max
689 689 423 157 0 689 423 157 85 0 1,002 302 169 120 507 423 423 2,101 1,400 833 -181 ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps
Max
570 570 350 130 0 570 350 130 70 0 830 250 140 100 420 350 350 1,740 1,160 690 -150
Altera Corporation
237 Preliminary
Stratix GX FPGA Family
Table 133. Stratix GX I/O Standard Output Delay Adders for Fast Slew Rate on Column Pins (Part 2 of 2) -5 Speed Grade Standard Min
GTL+ 3.3-V PCI 3.3-V PCI-X 1.0 Compact PCI AGP 1x AGP 2x CTT SSTL-3 class I SSTL-3 class II SSTL-2 class I SSTL-2 class II SSTL-18 class I SSTL-18 class II 1.5-V HSTL class I 1.5-V HSTL class II 1.8-V HSTL class I 1.8-V HSTL class II
-6 Speed Grade Min Max
-115 -241 -241 -241 -31 -31 53 95 -52 105 21 242 0 399 200 399 410
-7 Speed Grade Unit Min Max
-133 -277 -277 -277 -36 -36 61 109 -60 120 24 278 0 459 230 459 471 ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps
Max
-110 -230 -230 -230 -30 -30 50 90 -50 100 20 230 0 380 190 380 390
Table 134. Stratix GX I/O Standard Output Delay Adders for Fast Slew Rate on Row Pins (Part 1 of 2) -5 Speed Grade Standard Min
LVCMOS 2 mA 4 mA 8 mA 12 mA 24 mA 3.3-V LVTTL 4 mA 8 mA 12 mA 16 mA 24 mA
-6 Speed Grade Min Max
599 599 368 137 0 599 368 137 74 0
-7 Speed Grade Unit Min Max
689 689 423 157 0 689 423 157 85 0 ps ps ps ps ps ps ps ps ps ps
Max
570 570 350 130 0 570 350 130 70 0
238 Preliminary
Altera Corporation
Timing Model
Table 134. Stratix GX I/O Standard Output Delay Adders for Fast Slew Rate on Row Pins (Part 2 of 2) -5 Speed Grade Standard Min
2.5-V LVTTL 2 mA 8 mA 12 mA 16 mA 1.8-V LVTTL 2 mA 8 mA 12 mA 1.5-V LVTTL 2 mA 4 mA 8 mA CTT SSTL-3 class I SSTL-3 class II SSTL-2 class I SSTL-2 class II LVDS (1) LVPECL (1) PCML (1) HyperTransport Technology (1)
-6 Speed Grade Min Max
872 263 147 105 1,586 441 368 1,827 1,218 725 53 95 -52 105 21 -21 42 -63 74
-7 Speed Grade Unit Min Max
1,002 302 169 120 1,824 507 423 2,101 1,400 833 61 109 -60 120 24 -24 48 -73 85 ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps
Max
830 250 140 100 1,510 420 350 1,740 1,160 690 50 90 -50 100 20 -20 40 -60 70
Table 135. Stratix GX I/O Standard Output Delay Adders for Slow Slew Rate on Column Pins (Part 1 of 2) -5 Speed Grade I/O Standard Min
LVCMOS 2 mA 4 mA 8 mA 12 mA 24 mA
-6 Speed Grade Min Max
2,011 2,011 1,780 1,549 1,412
-7 Speed Grade Unit Min Max
2,312 2,312 2,046 1,780 1,623 ps ps ps ps ps
Max
1,911 1,911 1,691 1,471 1,341
Altera Corporation
239 Preliminary
Stratix GX FPGA Family
Table 135. Stratix GX I/O Standard Output Delay Adders for Slow Slew Rate on Column Pins (Part 2 of 2) -5 Speed Grade I/O Standard Min
3.3-V LVTTL 4 mA 8 mA 12 mA 16 mA 24 mA 2.5-V LVTTL 2 mA 8 mA 12 mA 16 mA 1.8-V LVTTL 2 mA 8 mA 12 mA 1.5-V LVTTL 2 mA 4 mA 8 mA GTL GTL+ 3.3-V PCI 3.3-V PCI-X 1.0 Compact PCI AGP 1x AGP 2x CTT SSTL-3 class I SSTL-3 class II SSTL-2 class I SSTL-2 class II SSTL-18 class I SSTL-18 class II 1.5-V HSTL class I 1.5-V HSTL class II 1.8-V HSTL class I 1.8-V HSTL class II
-6 Speed Grade Min Max
2,097 1,866 1,635 1,572 1,498 2,768 2,159 2,043 2,001 4,873 3,728 3,655 6,964 6,355 5,862 1,255 1,297 1,171 1,171 1,171 1,381 1,381 1,465 1,507 1,360 2,013 1,929 3,260 3,018 5,174 4,975 3,417 3,428
-7 Speed Grade Unit Min Max
2,411 2,145 1,879 1,807 1,722 3,182 2,482 2,349 2,300 5,604 4,287 4,203 8,008 7,307 6,740 1,442 1,90 1,346 1,346 1,346 1,587 1,587 1,684 1,732 1,563 2,314 2,218 3,748 3,470 5,950 5,721 3,929 3,941 ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps
Max
1,993 1,773 1,553 1,493 1,423 2,631 2,051 1,941 1,901 4,632 3,542 3,472 6,620 6,040 5,570 1,191 1,231 1,111 1,111 1,111 1,311 1,311 1,391 1,431 1,291 1,912 1,832 3,097 2,867 4,916 4,726 3,247 3,257
240 Preliminary
Altera Corporation
Timing Model
Table 136. Stratix GX I/O Standard Output Delay Adders for Slow Slew Rate on Row Pins -5 Speed Grade I/O Standard Min
LVCMOS 2 mA 4 mA 8 mA 12 mA 3.3-V LVTTL 4 mA 8 mA 12 mA 16 mA 2.5-V LVTTL 2 mA 8 mA 12 mA 16 mA 1.8-V LVTTL 2 mA 8 mA 12 mA 1.5-V LVTTL 2 mA 4 mA 8 mA CTT SSTL-3 class I SSTL-3 class II SSTL-2 class I SSTL-2 class II LVDS (1) LVPECL (1) 3.3-V PCML (1) HyperTransport technology (1) Note to Tables 131 through 136:
(1) These parameters are only available on the left side row I/O pins.
-6 Speed Grade Min Max
2,031 2,031 1,800 1,569 2,055 1,824 1,593 1,530 2,769 2,160 2,044 2,002 4,773 3,628 3,555 6,917 6,308 5,815 1,485 1,527 1,380 1,892 1,808 1,411 1,474 1,369 1,506
-7 Speed Grade Unit Min Max
2,335 2,335 2,069 1,803 2,363 2,097 1,831 1,759 3,183 2,483 2,350 2,301 5,489 4,172 4,088 7,954 7,253 6,686 1,707 1,755 1,586 2,175 2,079 1,622 1,694 1,573 1,731 ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps
Max
1,930 1,930 1,710 1,490 1,953 1,733 1,513 1,453 2,632 2,052 1,942 1,902 4,537 3,447 3,377 6,575 5,995 5,525 1,410 1,450 1,310 1,797 1,717 1,340 1,400 1,300 1,430
Altera Corporation
241 Preliminary
Stratix GX FPGA Family
Tables 137 and 138 show the adder delays for the column and row IOE programmable delays, respectively. These delays are controlled with the Quartus II software logic options listed in the Parameter column.
Table 137. Stratix GX IOE Programmable Delays on Column Pins -5 Speed Grade Parameter
Decrease input delay to internal cells
-6 Speed Grade Min Max
4,367 3,729 3,091 224 224 4,290 0 1,364 0 0 397 0 372 0 594 1,118 1,118 0 594 1,118 1,118 0 594 1,118 1,118
-7 Speed Grade Unit Min Max
5,022 4,288 3,554 257 257 4,933 0 1,568 0 0 456 0 427 0 683 1,285 1,285 0 683 1,285 1,285 0 683 1,285 1,285 ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps
Setting Min
Off On Small Medium Large
Max
3,970 3,390 2,810 212 212 3900 0 1,240 0 0 377 0 338 0 540 1,016 1,016 0 540 1,016 1,016 0 540 1,016 1,016
Decrease input delay to input register Decrease input delay to output register Increase delay to output pin Increase delay to output enable pin Increase output clock enable delay
Off On Off On Off On Off On Off On Small Large
Increase input clock enable Off delay On Small Large Increase output enable clock enable delay Off On Small Large
242 Preliminary
Altera Corporation
Timing Model
Table 138. Stratix GX IOE Programmable Delays on Row Pins -5 Speed Grade Parameter
Decrease input delay to internal cells
-6 Speed Grade Min Max
4,367 3,729 3,091 173 173 4,290 0 1,364 0 0 397 0 383 0 198 286 286 0 198 286 286 0 594 1,118 1,118
-7 Speed Grade Unit Min Max
5,022 4,288 3,554 198 198 4,933 0 1,568 0 0 456 0 441 0 227 328 328 0 227 328 328 0 683 1,285 1,285 ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps
Setting Min
Off On Small Medium Large
Max
3,970 3,390 2,810 164 164 3,900 0 1,240 0 0 377 0 348 0 180 260 260 0 180 260 260 0 540 1,016 1,016
Decrease input delay to input register Decrease input delay to output register Increase delay to output pin Increase delay to output enable pin Increase output clock enable delay
Off On Off On Off On Off On Off On Small Large
Increase input clock enable Off delay On Small Large Increase output enable clock enable delay Off On Small Large
Altera Corporation
243 Preliminary
Stratix GX FPGA Family
The scaling factors for output pin timing in Table 139 are shown in units of time per pF unit of capacitance (ps/pF). Add this delay to the combinational timing path for output or bidirectional pins in addition to the "I/O Adder" delays shown in Tables 131 through 136 and the "IOE Programmable Delays" in Tables 137 and 138.
Table 139. Output Delay Adder for Loading on LVTTL/LVCMOS Output Buffers LVTTL/LVCMOS Standards Conditions Parameter Value
24 mA 16 mA 3.3-V LVTTL 15 25 30 50 60 -
Output Pin Adder Delay (ps/pF)
2.5-V LVTTL - 18 25 35 - 75 1.8-V LVTTL - - 25 40 - 120 1.5-V LVTTL - - 35 80 160 LVCMOS 8 - 15 20 30 60
Drive Strength
12 mA 8 mA 4 mA 2 mA
SSTL/HSTL Standards Conditions
SSTL-3 Class I Class II 25 25
Output Pin Adder Delay (ps/pF)
SSTL-2 25 20 SSTL-1.8 25 25 1.5-V HSTL 25 20 1.8-V HSTL 25 20
GTL+/GTL/CTT/PCI Standards Conditions Parameter
VC C I O voltage level
Output Pin Adder Delay (ps/pF) Value
3.3 V 2.5 V GTL+ 18 15 GTL 18 18 CTT 25 PCI 20 AGP 20 -
244 Preliminary
Altera Corporation
Timing Model
Maximum Input & Output Clock Rates
Tables 140 through 142 show the maximum input clock rate for column and row pins in Stratix GX devices.
Table 140. Stratix GX Maximum Input Clock Rate for CLK[7..4] & CLK[15..12] Pins I/O Standard
LVTTL 2.5 V 1.8 V 1.5 V LVCMOS GTL GTL+ SSTL-3 class I SSTL-3 class II SSTL-2 class I SSTL-2 class II SSTL-18 class I SSTL-18 class II 1.5-V HSTL class I 1.5-V HSTL class II 1.8-V HSTL class I 1.8-V HSTL class II 3.3-V PCI 3.3-V PCI-X 1.0 Compact PCI AGP 1x AGP 2x CTT Differential HSTL LVDS LVPECL PCML HyperTransport technology
-5 Speed Grade -6 Speed Grade -7 Speed Grade
422 422 422 422 422 300 300 400 400 400 400 400 400 400 400 400 400 422 422 422 422 422 300 400 645 645 300 500 422 422 422 422 422 250 250 350 350 350 350 350 350 350 350 350 350 422 422 422 422 422 250 350 645 645 275 500 390 390 390 390 390 200 200 300 300 300 300 300 300 300 300 300 300 390 390 390 390 390 200 300 622 622 275 450
Unit
MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz
Altera Corporation
245 Preliminary
Stratix GX FPGA Family
Table 141. Stratix GX Maximum Input Clock Rate for CLK[0, 2, 9, 11] Pins & FPLL[8..7]CLK Pins I/O Standard
LVTTL 2.5 V 1.8 V 1.5 V LVCMOS GTL GTL+ SSTL-3 class I SSTL-3 class II SSTL-2 class I SSTL-2 class II SSTL-18 class I SSTL-18 class II 1.5-V HSTL class I 1.5-V HSTL class II 1.8-V HSTL class I 1.8-V HSTL class II 3.3-V PCI 3.3-V PCI-X 1.0 Compact PCI AGP 1x AGP 2x CTT Differential HSTL LVDS LVPECL PCML HyperTransport technology
-5 Speed Grade -6 Speed Grade -7 Speed Grade
422 422 422 422 422 300 300 400 400 400 400 400 400 400 400 400 400 422 422 422 422 422 300 400 717 717 400 717 422 422 422 422 422 250 250 350 350 350 350 350 350 350 350 350 350 422 422 422 422 422 250 350 717 717 375 717 390 390 390 390 390 200 200 300 300 300 300 300 300 300 300 300 300 390 390 390 390 390 200 300 640 640 350 640
Unit
MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz
Table 142. Stratix GX Maximum Input Clock Rate for CLK[1, 3, 8, 10] Pins (Part 1 of 2) I/O Standard
LVTTL 2.5 V
-5 Speed Grade -6 Speed Grade -7 Speed Grade
422 422 422 422 390 390
Unit
MHz MHz
246 Preliminary
Altera Corporation
Timing Model
Table 142. Stratix GX Maximum Input Clock Rate for CLK[1, 3, 8, 10] Pins (Part 2 of 2) I/O Standard
1.8 V 1.5 V LVCMOS GTL GTL+ SSTL-3 class I SSTL-3 class II SSTL-2 class I SSTL-2 class II SSTL-18 class I SSTL-18 class II 1.5-V HSTL class I 1.5-V HSTL class II 1.8-V HSTL class I 1.8-V HSTL class II 3.3-V PCI 3.3-V PCI-X 1.0 Compact PCI AGP 1x AGP 2x CTT Differential HSTL LVDS LVPECL PCML HyperTransport technology
-5 Speed Grade -6 Speed Grade -7 Speed Grade
422 422 422 300 300 400 400 400 400 400 400 400 400 400 400 422 422 422 422 422 300 400 645 645 300 645 422 422 422 250 250 350 350 350 350 350 350 350 350 350 350 422 422 422 422 422 250 350 645 645 275 645 390 390 390 200 200 300 300 300 300 300 300 300 300 300 300 390 390 390 390 390 200 300 640 640 275 640
Unit
MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz
Tables 143 and 144 show the maximum output clock rate for column and row pins in Stratix GX devices.
Table 143. Stratix GX Maximum Output Clock Rate for PLL[5, 6, 11, 12] Pins (Part 1 of 2) I/O Standard
LVTTL 2.5 V
-5 Speed Grade -6 Speed Grade -7 Speed Grade
350 350 300 300 250 300
Unit
MHz MHz
Altera Corporation
247 Preliminary
Stratix GX FPGA Family
Table 143. Stratix GX Maximum Output Clock Rate for PLL[5, 6, 11, 12] Pins (Part 2 of 2) I/O Standard
1.8 V 1.5 V LVCMOS GTL GTL+ SSTL-3 class I SSTL-3 class II SSTL-2 class I SSTL-2 class II SSTL-18 class I SSTL-18 class II 1.5-V HSTL class I 1.5-V HSTL class II 1.8-V HSTL class I 1.8-V HSTL class II 3.3-V PCI 3.3-V PCI-X 1.0 Compact PCI AGP 1x AGP 2x CTT Differential HSTL Differential SSTL-2 LVDS LVPECL PCML HyperTransport technology
-5 Speed Grade -6 Speed Grade -7 Speed Grade
250 225 350 200 200 167 167 200 200 150 150 250 225 250 225 350 350 350 350 350 200 225 200 500 500 350 350 250 200 300 167 167 150 150 200 200 133 133 225 200 225 200 300 300 300 300 300 200 200 200 500 500 350 350 250 200 250 125 125 133 133 167 167 133 133 200 200 200 200 250 250 250 250 250 200 200 167 500 500 350 350
Unit
MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz
Table 144. Stratix GX Maximum Output Clock Rate (Using I/O Pins) for PLL[1, 2] Pins (Part 1 of 2) I/O Standard
LVTTL 2.5 V 1.8 V
-5 Speed Grade -6 Speed Grade -7 Speed Grade
400 400 400 350 350 350 300 300 300
Unit
MHz MHz MHz
248 Preliminary
Altera Corporation
High-Speed I/O Specification
Table 144. Stratix GX Maximum Output Clock Rate (Using I/O Pins) for PLL[1, 2] Pins (Part 2 of 2) I/O Standard
1.5 V LVCMOS GTL GTL+ SSTL-3 class I SSTL-3 class II SSTL-2 class I SSTL-2 class II SSTL-18 class I SSTL-18 class II HSTL class I HSTL class II 3.3-V PCI 3.3-V PCI-X 1.0 Compact PCI AGP 1x AGP 2x CTT Differential HSTL LVDS LVPECL PCML HyperTransport technology
-5 Speed Grade -6 Speed Grade -7 Speed Grade
350 400 200 200 167 167 150 150 150 150 250 225 250 225 400 400 400 300 225 717 717 420 420 300 350 167 167 150 150 133 133 133 133 225 225 225 225 350 350 350 250 225 717 717 420 420 300 300 125 125 133 133 133 133 133 133 200 200 200 200 300 300 300 200 200 500 500 420 420
Unit
MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz
High-Speed I/O Specification
Table 145 provides high-speed timing specifications definitions.
Table 145. High-Speed Timing Specifications & Definitions (Part 1 of 2) High-Speed Timing Specification
tC fHSCLK tRISE
Definitions
High-speed receiver/transmitter input and output clock period. High-speed receiver/transmitter input and output clock frequency. Low-to-high transmission time.
Altera Corporation
249 Preliminary
Stratix GX FPGA Family
Table 145. High-Speed Timing Specifications & Definitions (Part 2 of 2) High-Speed Timing Specification
tFALL Timing unit interval (TUI)
Definitions
High-to-low transmission time. The timing budget allowed for skew, propagation delays, and data sampling window. (TUI = 1/(Receiver Input Clock Frequency x Multiplication Factor) = tC/w). Maximum/minimum LVDS data transfer rate (fHSDR = 1/TUI), non-DPA. Maximum/minimum LVDS data transfer rate (fHSDRDPA = 1/TUI), DPA. The timing difference between the fastest and slowest output edges, including tCO variation and clock skew. The clock is included in the TCCS measurement. The period of time during which the data must be valid in order to capture it correctly. The setup and hold times determine the ideal strobe position within the sampling window. SW = tSW (max) - tSW (min). Peak-to-peak input jitter on high-speed PLLs. Peak-to-peak output jitter on high-speed PLLs. Duty cycle on high-speed transmitter output clock. Lock time for high-speed transmitter and receiver PLLs.
fHSDR fHSDRDPA Channel-to-channel skew (TCCS)
Sampling window (SW)
Input jitter (peak-to-peak) Output jitter (peak-to-peak) tDUTY tLOCK
Table 146 shows the high-speed I/O timing specifications for Stratix GX devices.
Table 146. High-Speed I/O Specifications (Part 1 of 4) -5 Speed Grade Symbol
fHSCLK (Clock frequency) (LVDS, LVPECL, HyperTransport technology) fHSCLK = fHSDR / W fHSCLK_DPA
Notes (1), (2) -6 Speed Grade Min
10
-7 Speed Grade Unit Min
10
Conditions Min Typ
W = 1 to 30 for 717 Mbps W = 2 to 30 for > 717 Mbps 10
Max
717
Typ
Max
717
Typ
Max
624 MHz
74
717
74
717
74
717
MHz
250 Preliminary
Altera Corporation
High-Speed I/O Specification
Table 146. High-Speed I/O Specifications (Part 2 of 4) -5 Speed Grade Symbol
fHSDR Device operation (LVDS, LVPECL, HyperTransport technology)
Notes (1), (2) -6 Speed Grade Min
300 300 300 300 100 100 300 300 10
-7 Speed Grade Unit Min
300 300 300 300 100 100 300 300 10
Conditions Min Typ
J = 10 J=8 J=7 J=4 J=2 J = 1 (LVDS and LVPECL only) 300 300 300 300 100 100 300 300 10
Max
840 840 840 840 624 462 1000 1000 400
Typ
Max
840 840 840 840 624 462 840 840 400
Typ
Max
840 840 840 840 462 462 840 840 311 Mbps Mbps Mbps Mbps Mbps Mbps Mbps Mbps MHz
fHSDRDPA (LVDS, J=10 LVPECL) J=8 fHSCLK (Clock frequency) (PCML) fHSCLK = fHSDR / W fHSDR Device operation (PCML) W = 1 to 30
J = 10 J=8 J=7 J=4 J=2 J=1
300 300 300 300 100 100
400 400 400 400 400 250 6400
300 300 300 300 100 100
400 400 400 400 400 250 6400 0.44
300 300 300 300 100 100
311 311 311 311 300 200 6400 0.44
Mbps Mbps Mbps Mbps Mbps Mbps UI UI UI
DPA Run Length DPA Jitter Tolerance(p-p) DPA Minimum Eye opening (p-p) DPA Receiver Latency all data rates 0.56
0.44 0.56
0.56
5
9
5
9
5
9
Number of parallel CLK cycles
Altera Corporation
251 Preliminary
Stratix GX FPGA Family
Table 146. High-Speed I/O Specifications (Part 3 of 4) -5 Speed Grade Symbol
DPA Lock Time
Notes (1), (2) -6 Speed Grade Min Typ Max -7 Speed Grade Unit Min Typ Max
Conditions Min Typ
Standard Train -ing Pattern Trans -ition Density 256 256 256
Max
SPI4, CSIX
0000 10% 0000 0011 1111 1111
Number of repetitions Number of repetitions Number of repetitions Number of repetitions Number of repetitions 300 ps ps ps ps ps ps
Rapid 0000 25% IO 1111
256
256
256
1001 50% 0000
256
256
256
Misc
1010 100% 1010
256
256
256
0101 0101
256
256
256
TCCS SW
All PCML (J = 4, 7, 8, 10) PCML (J = 2) PCML (J = 1) LVDS and LVPECL (J = 1) LVDS, LVPECL, HyperTransport technology (J = 2 through 10) 750 900 1,50 0 500 440
200 750 900 1,500 500 440
200 800 1,200 1,700 550 500
Input jitter tolerance (peak-to-peak)
All
250
250
250
ps
252 Preliminary
Altera Corporation
High-Speed I/O Specification
Table 146. High-Speed I/O Specifications (Part 4 of 4) -5 Speed Grade Symbol
Output jitter (peak-to-peak) Output tRISE All LVDS HyperTransport technology LVPECL PCML Output tFALL LVDS HyperTransport technology LVPECL PCML tDUTY LVDS (J = 2 through 10) LVDS (J =1) and LVPECL, PCML, HyperTransport technology tLOCK
(1) (2)
Notes (1), (2) -6 Speed Grade Min Typ Max
160 80 110 90 80 80 110 90 105 47.5 45 110 170 130 110 110 170 130 140 50 50 120 200 150 135 120 200 160 175 52.5 55 80 120 100 80 80 110 100 110 47.5 45 110 170 135 110 110 170 135 145 50 50
-7 Speed Grade Unit Min Typ Max
200 120 200 150 135 120 200 160 175 52.5 55 ps ps ps ps ps ps ps ps ps % %
Conditions Min Typ Max
160 80 110 90 80 80 110 90 105 47.5 45 110 170 130 110 110 170 130 140 50 50 120 200 150 135 120 200 160 175 52.5 55
All
100
100
100
s
Notes to Table 146:
When J = 4, 7, 8, and 10, the SERDES block is used. When J = 2 or J = 1, the SERDES is bypassed.
Altera Corporation
253 Preliminary
Stratix GX FPGA Family
PLL Timing
Tables 147 through 149 describe the Stratix GX device enhanced PLL specifications.
Table 147. Enhanced PLL Specifications for -5 Speed Grades (Part 1 of 2) Symbol
fIN fINDUTY fEINDUTY tINJITTER tEINJITTER tFCOMP fOUT fOUT_EXT tOUTDUTY tJITTER tCONFIG5,6 tCONFIG11,12 tSCANCLK tDLOCK
Parameter
Input clock frequency Input clock duty cycle External feedback clock input duty cycle Input clock period jitter External feedback clock period jitter External feedback clock compensation time (3) Output frequency for internal global or regional clock Output frequency for external clock (2) Duty cycle for external clock output (when set to 50%) Period jitter for external clock output (5) Time required to reconfigure the scan chains for PLLs 5 and 6 Time required to reconfigure the scan chains for PLLs 11 and 12 scanclk frequency (4) Time required to lock dynamically (after switchover or reconfiguring any nonpost-scale counters/delays) (6) Time required to lock from end of device configuration PLL internal VCO operating range Clock skew between two external clock outputs driven by the same counter Clock skew between two external clock outputs driven by the different counters with the same settings Spread spectrum modulation frequency
Min
3 (1) 40 40
Typ
Max
684 60 60 200 (2) 200 (2) 6
Unit
MHz % % ps ps ns MHz MHz % ps or mUI
0.3 0.3 45
500 526 55 100 ps for >200 MHz outclk 20 mUI for <200 MHz outclk 289/fSCANCLK 193/fSCANCLK 22 100
MHz s
tLOCK fVCO tLSKEW tSKEW
10 300 50 75
400 800 (7)
s MHz ps ps
fSS
30
150
kHz
254 Preliminary
Altera Corporation
High-Speed I/O Specification
Table 147. Enhanced PLL Specifications for -5 Speed Grades (Part 2 of 2) Symbol
% spread tARESET
Parameter
Percentage spread for spread spectrum frequency (9) Minimum pulse width on areset signal
Min
0.4 10
Typ
0.5
Max
0.6
Unit
% ns
Table 148. Enhanced PLL Specifications for -6 Speed Grades Symbol
fIN fINDUTY fEINDUTY tINJITTER tEINJITTER tFCOMP fOUT fOUT_EXT tOUTDUTY tJITTER tCONFIG5,6 tCONFIG11,12 tSCANCLK tDLOCK
(Part 1 of 2) Max
650 60 60 200 (2) 200 (2) 6
Parameter
Input clock frequency Input clock duty cycle External feedback clock input duty cycle Input clock period jitter External feedback clock period jitter External feedback clock compensation time (3) Output frequency for internal global or regional clock Output frequency for external clock (2) Duty cycle for external clock output (when set to 50%) Period jitter for external clock output (5) Time required to reconfigure the scan chains for PLLs 5 and 6 Time required to reconfigure the scan chains for PLLs 11 and 12 scanclk frequency (4) Time required to lock dynamically (after switchover or reconfiguring any nonpost-scale counters/delays) (6) (10) Time required to lock from end of device configuration (10) PLL internal VCO operating range Clock skew between two external clock outputs driven by the same counter
Min Typ
3 (1) 40 40
Unit
MHz % % ps ps ns MHz MHz % ps or mUI
0.3 0.3 45
450 500 55 100 ps for >200 MHz outclk 20 mUI for <200 MHz outclk 289/fSCANCLK 193/fSCANCLK 22
MHz s
(8)
100
tLOCK fVCO tLSKEW
10 300 50
400 800 (7)
s MHz ps
Altera Corporation
255 Preliminary
Stratix GX FPGA Family
Table 148. Enhanced PLL Specifications for -6 Speed Grades Symbol
tSKEW
(Part 2 of 2) Max Unit
ps
Parameter
Clock skew between two external clock outputs driven by the different counters with the same settings Spread spectrum modulation frequency Percentage spread for spread spectrum frequency (9) Minimum pulse width on areset signal
Min Typ
75
fSS % spread tARESET
30 0.4 10 0.5
150 0.6
kHz % ns
Table 149. Enhanced PLL Specifications for -7 Speed Grade (Part 1 of 2) Symbol
fIN fINDUTY fEINDUTY tINJITTER tEINJITTER tFCOMP fOUT fOUT_EXT tOUTDUTY tJITTER tCONFIG5,6 tCONFIG11,12 tSCANCLK tDLOCK
Parameter
Input clock frequency Input clock duty cycle External feedback clock input duty cycle Input clock period jitter External feedback clock period jitter External feedback clock compensation time (3) Output frequency for internal global or regional clock Output frequency for external clock (2) Duty cycle for external clock output (when set to 50%) Period jitter for external clock output (5) Time required to reconfigure the scan chains for PLLs 5 and 6 Time required to reconfigure the scan chains for PLLs 11 and 12 scanclk frequency (4) Time required to lock dynamically (after switchover or reconfiguring any nonpost-scale counters/delays) (6) (10) Time required to lock from end of device configuration (10) PLL internal VCO operating range
Min
3 (1) 40 40
Typ
Max
565 60 60 200 (2) 200 (2) 6
Unit
MHz % % ps ps ns MHz MHz % ps or mUI
0.3 0.3 45
420 434 55 100 ps for >200 MHz outclk 20 mUI for <200 MHz outclk 289/fSCANCLK 193/fSCANCLK 22
MHz s
(8)
100
tLOCK fVCO
10 300
400 600 (7)
s MHz
256 Preliminary
Altera Corporation
High-Speed I/O Specification
Table 149. Enhanced PLL Specifications for -7 Speed Grade (Part 2 of 2) Symbol
tLSKEW tSKEW
Parameter
Clock skew between two external clock outputs driven by the same counter Clock skew between two external clock outputs driven by the different counters with the same settings Spread spectrum modulation frequency Percentage spread for spread spectrum frequency (9) Minimum pulse width on areset signal
Min
Typ
50 75
Max
Unit
ps ps
fSS % spread tARESET
30 0.5 10
150 0.6
kHz % ns
Notes to Tables 147 through 149:
The minimum input clock frequency to the PFD (fIN/N) must be at least 3 MHz for Stratix device enhanced PLLs. See "Maximum Input & Output Clock Rates" on page 245. tFCOMP can also equal 50% of the input clock period multiplied by the pre-scale divider n (whichever is less). This parameter is timing analyzed by the Quartus II software because the scanclk and scandata ports can be driven by the logic array. (5) Actual jitter performance may vary based on the system configuration. (6) Total required time to reconfigure and lock is equal to tDLOCK + tCONFIG. If only post-scale counters and delays are changed, then tDLOCK is equal to 0. (7) The VCO range is limited to 500 to 800 MHz when the spread spectrum feature is selected. (8) Lock time is a function of PLL configuration and may be significantly faster depending on bandwidth settings or feedback counter change increment. (9) Exact, user-controllable value depends on the PLL settings. (10) The LOCK circuit on Stratix PLLs does not work for industrial devices below -20C unless the PFD frequency > 200 MHz. See the Stratix FPGA Errata Sheet for more information on the PLL. (1) (2) (3) (4)
Altera Corporation
257 Preliminary
Stratix GX FPGA Family
Table 150 describes the Stratix GX device fast PLL specifications.
Table 150. Fast PLL Specifications for -5 & -6 Speed Grade Devices Symbol
fIN
Parameter
CLKIN frequency (for m = 1) (1) CLKIN frequency (for m = 2 to 19) CLKIN frequency (for m = 20 to 32)
Min
300 300/ m 10 9.4 9.375 300 40
Max
717 1,000/m 1,000/m 420 717 1,000 60 200
Unit
MHz MHz MHz MHz MHz MHz % ps % ps ps or mUI s Integer Integer ns
fOUT fOUT_EXT fVCO tINDUTY tINJITTER tDUTY tJITTER
Output frequency for internal global or regional clock (2) Output frequency for external clock VCO operating frequency CLKIN duty cycle Period jitter for CLKIN pin Duty cycle for DFFIO 1x CLKOUT pin (3) Period jitter for DIFFIO clock out (3) Period jitter for internal global or regional clock
45
55 80 100 ps for >200-MHz outclk 20 mUI for <200-MHz outclk
tLOCK m l0, l1, g0 tARESET
Time required for PLL to acquire lock Multiplication factors for m counter (3) Multiplication factors for l0, l1, and g0 counter (4), (5) Minimum pulse width on areset signal
10 1 1 10
100 32 32
Table 151. Fast PLL Specifications for -7 & -8 Speed Grades (Part 1 of 2) Symbol
fIN
Parameter
CLKIN frequency (for m = 1) (1), CLKIN frequency (for m = 2 to 19) CLKIN frequency (for m = 20 to 32)
Min
300 300/ m 10 9.375 9.4 300 40
Max
640 700/m 700/m 420 500 700 60 200
Unit
MHz MHz MHz MHz MHz MHz % ps
fOUT fOUT_EXT fVCO tINDUTY tINJITTER
Output frequency for internal global or regional clock (2) Output frequency for external clock VCO operating frequency CLKIN duty cycle Period jitter for CLKIN pin
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DLL Jitter
Table 151. Fast PLL Specifications for -7 & -8 Speed Grades (Part 2 of 2) Symbol
tDUTY tJITTER
Parameter
Duty cycle for DFFIO 1x CLKOUT pin (3) Period jitter for DIFFIO clock out (3) Period jitter for internal global or regional clock
Min
45
Max
55 80 100 ps for >200 MHz outclk 20 mUI for <200 MHz outclk
Unit
% ps ps or mUI s Integer Integer ns
tLOCK m l0, l1, g0 tARESET
Time required for PLL to acquire lock Multiplication factors for m counter (4) Multiplication factors for l0, l1, and g0 counter (4), (5) Minimum pulse width on areset signal
10 1 1 10
100 32 32
Notes to Tables 150 and 151:
(1) (2) See "Maximum Input & Output Clock Rates" on page 245. When using the SERDES, high-speed differential I/O mode supports a maximum output frequency of 210 MHz to the global or regional clocks (i.e., the maximum data rate 840 Mbps divided by the smallest SERDES J factor of 4). This parameter is for high-speed differential I/O mode only. These counters have a maximum of 32 if programmed for 50/50 duty cycle. Otherwise, they have a maximum of 16. High-speed differential I/O mode supports W = 1 to 16 and J = 4, 7, 8, or 10.
(3) (4) (5)
DLL Jitter
Table 152 reports the jitter for the DLL in the DQS phase shift reference circuit.
Table 152. DLL Jitter for DQS Phase Shift Reference Circuit Frequency (MHz)
197 to 200 160 to 196 100 to 159 100 300 500
DLL Jitter (ps)
For more information on DLL jitter, see the DDR SRAM section in the Stratix Architecture chapter in the Stratix Device Handbook, Volume 1.
Software
Stratix GX devices are supported by the Altera Quartus II design software, which provides a comprehensive environment for system-on-aprogrammable-chip (SOPC) design. The Quartus II software includes hardware description language and schematic design entry, compilation and logic synthesis, full simulation and advanced timing analysis,
Altera Corporation
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Stratix GX FPGA Family
SignalTap logic analysis, and device configuration. See the Design Software Selector Guide for more details on the Quartus II software features. The Quartus II software supports the Windows 2000/NT/98, Sun Solaris, Linux Red Hat v6.2 and HP-UX operating systems. It also supports seamless integration with industry-leading EDA tools through the NativeLink(R) interface.
Device Pin-Outs Ordering Information Revision History
Device pin-outs for Stratix GX devices will be released on the Altera web site (www.altera.com). Ordering information will be available in a future version of this data sheet.
The information contained in the Stratix GX FPGA Family data sheet version 2.2 supersedes information published in previous versions.
Version 2.2
The following changes were made to the Stratix GX FPGA Family data sheet version 2.2:

Updated Figures 37, 38, and 125. Updated Tables 61, 66, 102, 109, 140, 141, and 143. Updated the section "Phase Compensation FIFO Buffer" on page 31. Updated the section "Logic Array Blocks" on page 61. Updated the section "Clock Switchover" on page 144. Updated the section "Lock Detect" on page 152. Updated the section "Advanced Clear & Enable Control" on page 153. Updated the section "I/O Structure" on page 157. Updated the section "Power Sequencing & Hot Socketing" on page 182. Removed Txz, Tzx, Tzxpll, and Txzpll parameters because of errors in data. These parameters will be added in when new data is available.
Version 2.1
The following changes were made to the Stratix GX FPGA Family data sheet version 2.1:
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Revision History

Updated "Transceiver Blocks" section. Added "Stratix GX Clocking" section. Updated "Source-Synchronous Signaling with DPA" section. Updated termination information. Updated Figure 63. Updated timing parameters. Added Stratix GX transceiver parameters. Updated Gigabit Ethernet support information.
Altera Corporation
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Stratix GX FPGA Family
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Altera Corporation

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